Remote Control Application and Troubleshooting of ADLINK PCIe-8560/PXI-8565 Expansion Kit

In automated testing systems, military aerospace equipment, and high-density data acquisition applications, the PXI platform has become the industry standard due to its modularity, high bandwidth, and robust structure. However, PXI chassis typically require collaboration with host controllers (such as embedded controllers or remote PCs), and traditional solutions are limited by the PCI bus distance (usually not exceeding 0.3 meters), resulting in the host having to be close to the object being tested, which is extremely inconvenient in high temperature, vibration, or narrow space environments. The PCIe-8560 and PXI-8565 expansion kits launched by ADLINK utilize the high-speed differential signal of PCI Express to achieve a remote connection of up to 7 meters between the host and PXI chassis, while maintaining complete hardware and software transparency. This article will provide engineers with a complete practical guide from the aspects of system architecture, installation configuration, signal integrity tuning, critical jumper settings, power on timing, and common compatibility issues, to help them efficiently deploy this expansion solution and quickly locate faults.

System architecture and transparency advantages

PCIe-8560 (host PCIe card) and PXI-8565 (PXI chassis system slot controller) are connected through shielded twisted pair cables to form a point-to-point PCIe x1 link, with an effective signal rate of 2.5 Gbps (per direction). The PXI-8565 has a built-in PCIe to PCI bridge that converts PCIe protocol to a standard 32-bit/33MHz PCI bus, driving all peripheral modules on the PXI backplane. Due to the complete transparency of the entire bridging process to the operating system and drivers, the PXI module is recognized as being directly plugged into the host's internal PCI slot, without the need to install any additional software or drivers, greatly reducing deployment complexity.

The typical application scenarios of this kit include:

Semiconductor testing sorting machine: Keep the PXI instrument away from the high-temperature area of the production line and place the host at the operator's workstation.

Vehicle or onboard testing: The host is located in the control room, and the PXI chassis is close to the sensors to reduce the attenuation of long line analog signals.

High density digital I/O system: Utilizing PXI chassis multi slot expansion, the host only needs one PCIe slot.

Hardware installation steps and key precautions

1. Installation of PCIe-8560 on the host side

Turn off the host power, select any x1, x4, x8, or x16 PCIe slot, and insert the PCIe-8560 (low profile size 68.9mm × 86.65mm, power consumption only) 3.3V@210mA ）.

Attention: This card is an x1 gold finger and can be installed in any PCIe slot without external power supply.

2. Installation of PXI-8565 on the PXI chassis end

It must be installed in the system slot, not the peripheral slot. Taking ADLINK PXIS-2508 as an example, the system slot is usually located on the leftmost side or in a specific identification position.

Before installation, ensure that the chassis is grounded, wear an anti-static wrist strap, and secure the panel screws to ensure good grounding and mechanical stability.

3. Expand cable connections

The standard packaging provides 3-meter shielded wire (ACL-EXPRESS-3), as well as 1-meter and 7-meter options. When connecting, tighten the screws at both ends to ensure good grounding of the shielding layer.

It is strictly prohibited to plug or unplug cables when the system is powered on, otherwise it may cause the host blue screen or PXI chassis to lose control, and even damage hardware.

Power on timing - key and often overlooked details

Since PCIe-8560 is essentially a PCIe to PCI bridge, during the host POST (power on self-test) phase, the BIOS scans the PCI bus and allocates resources (I/O, memory, etc.) IRQ）。 To enable the BIOS to correctly recognize all modules in the remote PXI chassis, the following sequence must be strictly followed:

First, turn on the PXI chassis power (while the host is still turned off).

Wait for a few seconds until the PXI backplane stabilizes power supply.

Turn on the host power again.

Reason: When enumerating PCI devices, the host BIOS needs to detect the presence of the PXI-8565 bridge and its subordinate devices. If the chassis is not powered on and the bridge cannot respond to configuration requests, the BIOS will ignore the bus segment, causing it to be unrecognizable even if the chassis is powered on in the future. Once this situation occurs, it is necessary to power off and restart at the same time, and then power on again in the correct order.

The shutdown sequence is the opposite:

First, shut down the host operating system and power off.

Turn off the PXI chassis power again.

If this order is violated (shut down the PXI chassis first), the host PCI bridge will detect bus hot unplugging, which may cause system crashes or data loss.

Signal integrity optimization - S1/S2 equalizer adjustment

In long-distance (especially 7-meter) transmission, high-frequency signals will be attenuated due to cable losses, while inter symbol interference (ISI) will occur. The PCIe-8560 board is equipped with a programmable signal equalizer, output swing, and de emphasis adjustment circuit, which are tuned through two sets of 4-bit DIP switches (S1 for the transmit channel and S2 for the receive channel). All adjustments must be applied simultaneously to S1 and S2 to ensure bidirectional link symmetry.