ADLINK PCIe-CPL64 Image Acquisition Card Hardware Trigger and Encoder Application

ADLINK PCIe-CPL64 Camera Link Image Acquisition Card Hardware Trigger and Encoder Application Analysis

In the field of machine vision and industrial inspection, real-time acquisition and transmission of image data from high-resolution and high frame rate cameras has always been a core challenge in system design. The Camera Link interface, with its high-speed LVDS signal and mature standard protocol, has become the preferred connection method for line scan and area scan cameras. The ample bandwidth provided by the PCI Express bus provides a reliable transmission channel for multi-channel or high-resolution image data. ADLINK PCIe-CPL64, as a PCIe x4 interface based Camera Link frame acquisition card, supports dual Base configuration or single Medium configuration, with a maximum pixel clock of 85MHz. It integrates encoder input, multi trigger I/O, and Power over Camera Link (PoCL) functions, providing a high-performance and flexible image acquisition platform for applications such as semiconductor inspection, PCB automatic optical inspection (AOI), and printing quality monitoring. This article will provide a detailed technical reference for system integration engineers from the aspects of hardware architecture, trigger mode, encoder position synchronization, software configuration, and practical debugging points.

Product positioning and core specifications

PCIe-CPL64 is positioned for machine vision systems that require high bandwidth, multiple camera access, or complex external synchronization. Its core features include:

Interface and configuration: PCI Express x4, supports simultaneous acquisition of two independent Base mode Camera Link cameras (dual Base) or one Medium mode camera (single Medium). In dual Base mode, the total bandwidth can reach 255MB/s per channel, while in Medium mode it can reach 320MB/s.

Image Cache: Onboard 128MB 200MHz DDR SDRAM, used to buffer image data and prevent frame loss caused by bus congestion.

PoCL support: Each channel can output+12V/1A power supply, automatically detect PoCL compatible cameras and provide power, while also having overcurrent protection.

External I/O: 4-channel TTL digital input, 4-channel digital output (open drain, can be pulled up to+5V), 2-channel TTL trigger input, 2-channel TTL trigger start input, 2-channel exposure output, and encoder differential input (RS422, A/B/Z three-phase, up to 1MHz).

Camera control: CC1~CC4 LVDS control signals, configurable as pulse or level outputs, used to control camera exposure, line period, etc.

This card supports Windows XP/Vista and subsequent systems (UAC needs to be disabled), and provides a complete API library (C++, C #, VB.net) and CamCreator configuration tool, greatly simplifying system development and debugging.

Hardware layout and key connectors

PCIe-CPL64 adopts the standard PCIe half height card size (167.65mm × 111.15mm), and its main interfaces include:

CN1 and CN2: Two MDR26 Camera Link connectors, corresponding to channel 0 and channel 1 respectively. In dual Base mode, each connector is connected to a Base camera; In Medium mode, only CN1 is connected to one Medium camera (occupying two data channels).

The CN3: 25 pin D-SUB connector integrates encoder input, trigger input/output, universal DI/DO, and exposure output. For specific pin definitions, please refer to Table 2-1 in the manual. Encoder A-phase/B-phase/Z-phase differential pairs, TTL trigger input, line trigger enable, etc. are all led out through this connector.

SW1:4 DIP switch, used to set Card ID (0~15), supports multi card coexistence.

SW2: A 4-bit independent switch used to select whether DO0~DO3 should be internally pulled up to+5V (through a 10k Ω resistor) for direct driving of PNP or NPN loads.

JP1: Used to select the input level of Z-phase encoder as TTL or RS422, default RS422.

LED indicator lights: LED3/LED5 respectively indicate the PoCL power supply status of channels A/B, and LED4/LED6 indicate the acquisition status (flashing indicates image capture).

Note: This card only supports x4, x8, or x16 PCIe slots. If inserted into an x16 slot that only supports VGA, the speed will decrease to x1, affecting performance.

PoCL Power Supply and Cable Safety

Power over Camera Link is an important extension of the Camera Link standard, allowing power to be supplied to the camera through data cables and reducing external power wiring. PCIe-CPL64 can provide+12V/1A power per channel and has automatic detection function (set to 0: Auto Detect through SetPowerState). In this mode, the card will detect whether the connected camera supports PoCL. If it supports PoCL, power will be supplied; otherwise, power will not be supplied. In addition, it can also be manually set to "Short ground" or "Short+12V" mode, but the latter is only for use with PoCL cameras, and misconnecting a non PoCL camera may cause damage.

Practical suggestion: When connecting an unknown camera for the first time, it is recommended to use Auto Detect mode and observe the status of LED3/LED5 to confirm that the power supply is normal. If the power consumption of the camera exceeds 1A, an external independent power supply is required, otherwise overcurrent protection may be triggered.

Trigger mode synchronized with encoder

PCIe-CPL64 supports multiple triggering methods to meet the different requirements of line array scanning and area array scanning. The triggering mode can be configured through the AKS aptureMode function or the CaptureMode field in the Camera File

Free Run: Continuous collection, not limited by external triggers, suitable for scenes with stable lighting and continuous motion.

Line Area Trigger: External TTL or RS422 trigger signals control the acquisition of each line or frame. The trigger source can be pin9/pin10 (TTL) or pin1-4 (RS422 differential) of CN3. SetLineAreaTriggerPolarity can be used to set the rising or falling edge trigger, and LineAreaTriggerStartEnable can be enabled to make the trigger signal only valid during the high-level enable period.

Encoder Input: Only applicable to linear scanning cameras, it controls line acquisition through pulses generated by an external encoder (A/B/Z three-phase) to achieve precise synchronization between image lines and physical motion positions. This is a key function for applications such as print inspection and roll surface inspection.

Encoder triggers detailed mechanism

The encoder input supports three modes (set through SetEncoder Input Mode):

A Phase: When an edge (rising or falling) of A phase is detected, a row of data acquisition is triggered.

AB Phase: Determine the direction of motion (CW or CCW) based on the phase difference between phase A and phase B. After each complete orthogonal period, trigger one line to achieve frequency doubling counting (1x/2x/4x).

ABZ Phase: The Z phase is used as the reference zero signal. When the Z phase is at a high level, the A/B phase starts counting and is used to establish an absolute position reference.

In addition, there are two key counters:

Encoder Delay Count: Ignoring the first N encoder pulses after starting the acquisition process, used to skip the acceleration phase during motion startup.

Encoder Compare Count: Each count of N valid pulses triggers a line acquisition, which is equivalent to pulse division. It is suitable for scenarios where high-resolution encoders need to reduce line density.

For example, if the encoder outputs 1000 pulses per millimeter and the camera needs to capture 200 lines per millimeter, set Encoder Compare Count to 5, which means capturing one line every 5 pulses to achieve a resolution of 5 μ m/line.

The counting direction of the encoder can be set to CW or CCW through SetEncoder Input Direction to accommodate differences in installation direction. There is also a hardware counter in the card (which can be read through the FHIR ncoderCounterValue), making it easy for software to monitor the current location.

Line triggered start signal

For applications that require external enable signals (such as starting data collection only after the material passes through the sensor), Line Trigger Start input (CN3 pin11/12) can be used. When this signal is at a high level, the trigger signal is allowed, otherwise it is blocked. Refer to Figure 2-4 in the manual for the timing diagram, which can effectively avoid image acquisition in invalid areas.

GPIO and External Control

PCIe-CPL64 provides 4 TTL digital inputs (DI0-3) and 4 open drain digital outputs (DO0-3). DI supports event triggering (enabled through SetDIEvent), and callback functions can be called when DI status changes to respond to external alarms or synchronization signals. DO is an open drain output, with no pull-up by default, but it can be enabled to internally pull up 10k Ω to+5V through SW2, making it convenient to directly drive low-power loads (maximum current of 100mA). If a large current needs to be driven, it is recommended to connect an external transistor or relay.

In addition, there are two Exposure Out signals that can directly output pulses synchronized with the internal exposure timing, used to control the external light source flicker and avoid heat generation and energy waste caused by continuous lighting.

Camera File Configuration and Parameter Explanation

PCIe-CPL64 uses a text-based Camera File (. cam) to store camera specific parameters, including sensor size, pixel count, tap count, trigger mode, CC1/CC2 control, etc. Users can load or modify it through the CamCreator tool, or manually edit it. The following key parameters are highlighted:

Sensor Tap: The number of camera output channels, such as single tap, dual tap, quad tap, etc. It is necessary to coordinate with SensorTapPlacement to specify the data arrangement order (such as odd sequence, start+middle, etc.).

PixelSize: The number of significant bits per pixel (8/10/12/14/16/24/30/36 bits). Note that if Tap=3 and PixelSize=8, it is in RGB24 color format.

PixelFormat: Unpack (raw data with padding bytes) or Pack (compressed without padding). Pack format reduces data volume but consumes CPU for reassembly.

CC1/CC2 Type: can be set as Pulse (pulse output) or DO (level output). In pulse mode, the pulse width and negative pulse width can be set to control the camera exposure or line period.

LVALEnable/DVALEnable: Camera Link standard signal line, used to indicate valid pixels or valid data, must be correctly enabled according to the camera manual.

The card also provides the dDataBits function, which can return the actual bus bit width occupied by each pixel, making it easier to calculate the required memory. The size of the system buffer can be adjusted through tSystemBufferCount, with a default of 4 frames. It is recommended to increase it appropriately according to the image resolution and frame rate to prevent frame loss.

Key points of development environment and API usage

ADLINK provides the Cpl64.dll dynamic library, along with accompanying header files (Cpl64. h) and import libraries (Cpl64. lib). Developers need to include header files and link library files. The basic calling process is as follows:

Cpl64_GetDeviceCount() retrieves the number of cards.

Cpl64_SpenDevice (CardID, Channel) opens the specified channel (0 or 1) and returns a handle.

Cpl64_LoadCamFile (Handle, "camera. cam") loads the camera file.

If using callback method, call Cpl64_Setcallback (Handle, EventType, VNet) to register image ready or DI event callback.

Cpl64_StartCapture (Handle, TotalFrames) starts collecting (TotalFrames=0 indicates continuous).

Process image data in callbacks or use Cpl64_SnapShot for single frame capture.

Cpl64_StopCapture stops collecting, Cpl64_CloseDevice releases resources.

For serial communication (used for camera parameter settings), an independent clallserial library is required, and the initialization, read-write, and shutdown processes are similar to standard serial port operations.

Common error codes: Returning -3 indicates an invalid handle, -7 indicates the device is not turned on, and -10 indicates a driver issue. It is necessary to check the driver installation and system version.

Practical tips for CamCreator tool

CamCreator is a debugging tool, with its interface divided into device panel, camera panel, parameter panel, counter panel, I/O and soft trigger panel, and display window.

Dynamic parameter tuning: Modifying XOffset, YOffset, SensorWidth, etc. in the parameter panel will take effect in real time, making it easy to quickly verify the camera output range.

Trigger Test: DI/DO can be directly read and written in the I/O panel, and software Trigger Out can be triggered to test the response of light sources or external devices.

Counter monitoring: Encoder Counter and Line Counter display the current pulse count, which can be used to verify the encoder wiring and direction.

Image analysis: Supports "Focus Value" to display the pixel value curve of the selected row, and "Zoom In" to zoom in on local areas for checking focus and image quality.

Note that UAC needs to be disabled on Windows Vista and above systems, otherwise CamCreator may not be able to access the hardware correctly.

Common problems in installation and debugging

1. Device Manager cannot find the device after driver installation

Confirm that the PCIe slot is powered on normally and try replacing the slot.

Check if PCIe channel is disabled in BIOS settings.

Under Windows 7, it is necessary to manually specify the driver path ( ADLINK  cpl64  Driver).

2. Collecting images with blurred or misaligned screens

Check if the Camera Link cable is in good condition, with a recommended maximum length of no more than 10 meters.

Confirm that parameters such as SensorWidth, SensorHeight, TapPlacement match the actual output of the camera.

Adjust the DataValidDelay parameter to solve the phase shift of data sampling.

3. Encoder triggers no response

Check if the polarity of the differential signal of CN3 encoder is correct (A+and A -, B+and B -).

Confirm that CaptureMode is set to Encoder Input and ScanMode is set to LineScan.

Observe whether the Encoder CounterValue increases with the rotation of the encoder. If there is no change, check the wiring and JP1 level settings.

4. The PoCL power supply indicator light is not on

Confirm that the camera supports PoCL and the cable is PoCL compatible (all pins are complete).

Attempt to set PowerState to "Short+12V" for forced power supply (proceed with caution).

Selection and System Design Suggestions

PCIe-CPL64 is suitable for applications that require medium bandwidth (up to 85MHz pixel clock) and high synchronization requirements. For higher bandwidth or higher pixel clocks (such as above 85MHz), updating models such as PCIe-CPL64v2 or PCIe-CPL128 may be considered. But the dual Base mode of the card can simultaneously connect two cameras, suitable for binocular stereo vision or multi station detection, and the flexibility of encoder input and triggering makes it outstanding in linear array applications such as printing, textile, battery electrode detection, etc.

Attention should be paid to the following during design:

Calculate bus bandwidth: The total data rate in dual Base mode is about 255MB/s, and the theoretical bandwidth of PCIe x4 is 1GB/s. Therefore, the bottleneck lies in the Camera Link interface, not the bus.

Memory allocation: Allocate buffers reasonably according to the Set System Buffer Count formula to avoid memory overflow.

Cable length: If it needs to exceed 10 meters, it is recommended to use a Camera Link repeater or fiber optic converter.