Advanced triggering and multi card synchronization of ADLINK PCIe-CPL64V image acquisition card

Advanced triggering and multi card synchronization application of ADLINK PCIe-CPL64V image acquisition card

In the field of high-speed machine vision and industrial inspection, the Camera Link interface has long dominated high-end camera connectivity due to its high bandwidth, anti-interference, and standardization advantages. With the continuous improvement of image resolution and frame rate, traditional PCIe x4 acquisition cards are gradually facing challenges in throughput and synchronization accuracy. The PCIe-CPL64V series launched by ADLINK adopts PCIe Gen3 x4 architecture, supports Base/Medium/Full full configuration Camera Link, has a maximum aggregated data transfer rate of 850 MB/s, and integrates advanced functions such as multi card synchronization, programmable trigger chain, encoder position trigger, etc., providing a highly flexible hardware platform for linear scanning, 3D detection, and high-speed AOI systems. This article will provide engineers with a system level application reference from the dimensions of hardware architecture, trigger logic, CAM file configuration, multi card synchronization mechanism, and common debugging methods, to help them quickly solve difficult problems in practical deployment.

Product positioning and core upgrade highlights

PCIe-CPL64V is a fully upgraded version of the previous generation PCIe-CPL64, with major improvements including:

Doubling bus bandwidth: PCIe Gen3 x4 provides a theoretical bandwidth of approximately 3.9 GB/s, with an actual image transfer rate of 850 MB/s, making it easy to meet the full bandwidth requirements of 85MHz pixel clock in Full configuration (80 bits) (approximately 680 MB/s).

Memory expansion: Onboard 512 MB DDR cache, supporting longer burst collection and frame buffer queues, reducing the risk of frame loss.

I/O isolation enhancement: Provides 4-channel isolated digital input/output (500Vrms isolation), supports 10kHz input and 500kHz output, and adapts to strong interference environments in industrial sites.

Encoder interface upgrade: Differential isolated encoder input, supporting up to 20MHz (4x AB mode), compatible with multiple encoder protocols such as CW/CCW, OUT/DIR, etc.

Multi card synchronization: Supports up to 4 cards for synchronization, with a synchronization delay of less than 100ns, meeting the requirements of multi camera collaborative acquisition.

These features make it particularly suitable for high demand scenarios such as printing quality inspection, defect scanning for flat panel displays, and visual positioning for high-speed surface mount machines.

Trigger architecture: flexible and programmable signal chain

The triggering system of PCIe-CPL64V is its core competitiveness, and users can configure complex triggering chains through CAM files or APIs. The overall diagram can be found in Chapter 4 of the manual, and the core modules include:

1. Trigger Source Selection

Each output channel (4 DO and 2 CC control lines) can independently select trigger sources, including:

DI0~DI3 events: External isolated input, can be set with rising/falling edge triggering, and equipped with a debounce filter (0/200/500/800ns).

Encoder comparison event: triggered when the encoder count reaches the preset Compare Count.

Multi card synchronization event: The synchronization signal broadcasted by the main card, and the slave card listens for the event.

Software trigger: manually triggered through API.

This multi-source selection mechanism allows users to flexibly combine external sensors, encoder positions, and software instructions to adapt to complex automation processes.

2. Trigger Delay

Each output channel can be independently configured with a delay mode:

Timer mode: Set a fixed delay time in units of 1 μ s (maximum approximately 16.7 seconds).

Encoder mode: Delay the specified number of encoder pulses (up to 32 bits) to achieve position dependent delay, such as waiting for a fixed physical distance to trigger camera exposure after detecting material edges.

3. Re trigger

This function automatically generates a predefined number of output pulses after a single external trigger, especially suitable for linear scanning cameras. For example, when an external sensor triggers once, 1024 CC1 pulses (one per line) need to be continuously sent to the camera to complete the acquisition of one frame of image. By setting Retrigger. Enable=True and specifying the number and interval of triggers (encoder count or timer), the hardware automatically completes the entire sequence without CPU intervention, greatly improving real-time performance.

4. Output PWM generation

Each DO and CC channel can be configured for manual mode or trigger mode. In trigger mode, the high-level and low-level widths of the output pulse can be independently set (1 μ s resolution) for precise control of light source flicker or camera exposure timing.

This modular design allows engineers to achieve full chain timing matching from external events to camera control without writing complex logic, solely through CAM files.

CAM file configuration: from templates to customization

The CAM file (in. ini format) is the core configuration file of PCIe-CPL64V, which defines all operational parameters such as image format, trigger behavior, encoder parameters, I/O mapping, etc. Users can load templates and modify them through the CamCreator tool, or directly edit text files. The following focuses on analyzing several chapters that are prone to errors or require special attention.

1. [ImageFormat] Image format and bandwidth limitations

SensorWidth/SensorHeight: Specific alignment multiple requirements must be met, for example, when Mono8 x 1/2/4/8tap, the width must be a multiple of 32; When Mono10 x 8tap, the width needs to be a multiple of 320. If it does not meet the requirements, an error will be reported when the collection starts.

CameraConfiguration: Select Base, Medium, or Full based on the actual connected camera configuration, corresponding to different data bit widths and required cable numbers (see manual table). Incorrect configuration can cause abnormal status of LED7 (orange flashing indicates error).

TapPlacement: It is necessary to match the actual output mode of the camera (single/double/four/eight/ten tap), otherwise the image arrangement will be disordered.

Practical tip: Use LED7 status indicator light to quickly diagnose configuration: Green constant light=Full, green flashing (2Hz)=Medium, orange constant light=Base, orange flashing=Abnormal, off=No camera detected.

2. [TriggerInput] triggers input debounce

When using mechanical switches or relay contacts as trigger sources, shaking may cause false triggering. Setting DebounceTime (200/500/800ns) can effectively filter out glitches, but it should be noted that a long debounce time may delay the response and needs to be balanced based on the actual signal frequency.

3. [Encoder Input] Encoder mode and comparison value

Mode: Supports multiple modes such as AB phase X1/X2/X4, CW/CCW, OUT/DIR, etc., and needs to match the output type of the encoder.

Comparing Count: When the encoder count reaches this value, a comparison event is generated, which can be used as one of the trigger sources. Real time position can be monitored by reading the status parameters of Encoder Counter.

4. [Retrigger] Re trigger setting instance

Assuming a linear camera is used, the rising edge of the external DI0 triggers one frame acquisition, requiring 2048 lines per frame, and the encoder triggers one line every 10 pulses. Then configure:

text

[TriggerOutputTrigSrc]

DO0TriggerSource=DI0 # DI0 as initial trigger

[Retrigger]

Port0CC1RetriggerEnable = True

Port0CC1Mode = EncoderMode

Port0CC1TriggerNums = 2048

Port0CC1Interval=10 # CC1 is triggered every 10 encoder pulses

In this way, when DI0 is triggered once, the hardware automatically outputs 2048 CC1 pulses to the camera continuously at intervals of encoder pulses, completing the entire frame acquisition.

Multi card synchronization: precise timing and low latency

When multiple cameras are needed for simultaneous shooting (such as binocular stereo vision or multi angle detection), PCIe-CPL64V provides inter board synchronization mechanism, supporting up to 4 cards for synchronization with synchronization jitter less than 100ns.

Hardware connection: All cards are cascaded through a CN4 dedicated ribbon cable, distinguishing between master and slave cards. The main card's CN4 outputs a synchronization signal, and the secondary card's CN4 receives the signal.

CAM file configuration:

Master card setting [MultiCardSync] Mode=Master

From Card Settings [MultiCardSync] Mode=Slave

In [MultiCardTrigSrc], the master card selects the trigger source (such as DI0), and the slave card selects TriggerSource=MultiCardSync.

Power on timing: The master card needs to start collecting data before the slave card to ensure stable synchronization signals. The current mode (1=Master, 0=Slave) can be verified through the state parameter MultiCardSync Mode.

Troubleshooting: If synchronization fails, check if the CN4 cable is locked, if the card ID conflicts (SW1 must be unique), and if the main card is generating synchronization events normally (observe LED2: the main card is always red and the slave card is always green). If LED2 on the card does not light up, it means that no synchronization signal has been received and the hardware connection or CAM file configuration needs to be checked.

PoCL power supply and safety testing

PCIe-CPL64V supports Power over Camera Link, and each SDR interface can output+12V/0.8A. The automatic detection function can identify non PoCL cables or cameras to avoid damage. However, some PoCL devices may not comply with standard timing, causing voltage startup or drop beyond the tolerance range. In this case, the PoCL SafePower Status parameter will report an error (non-zero value), and the corresponding Clock Startup Time Tolerance, Clock Drop Out Time Tolerance, and Voltage Drop Duration Tolerance can be manually adjusted (in μ s) to relax the detection conditions. These tolerances can be pre-set in the CAM file to be compatible with non-standard devices.

Attention: If the PoCL power indicator light (LED next to LED7) does not light up, first check if the cable is PoCL compatible (all 26 cores are intact), and then try to force the PowerState setting (but be cautious).

State parameters and debugging tools

Chapter 6 of the manual lists a wealth of status registers, which can be read through AVSAdvancedConfigRead and are extremely useful for on-site debugging:

DataStreamStatus: Indicates whether the FPGA is receiving data from the front-end and transmitting data to the host, quickly locating data flow blocking points.

DelayBufferCount/Overflow: Each trigger delay module has an internal buffer that records the number of trigger events that have not yet been output. If the overflow exceeds 255, it indicates that the triggering frequency is too high or the delay setting is too long, and the parameters need to be adjusted.

EventCount/DropCount: Each trigger source and output channel has independent event and dropout counts. A non-zero DropCount indicates that the trigger signal has been lost, and it is necessary to check the quality of the front-end signal or increase the buffer.

Camera Link Configuration: Real time display of the currently detected configuration (Base/Medicine/Full/Error), corresponding to the status of LED7.

By utilizing these states, engineers can quickly diagnose bottlenecks in the trigger chain without the need for an oscilloscope, significantly reducing the debugging cycle.

Common Problems and Troubleshooting Guide

1. Collecting images with blurred screens or incorrect lines

Check if TapPlacement matches the actual output of the camera (such as double tap odd order, starting center, etc.).

Verify if SensorWidth meets the alignment requirements (see warning in section 5.1.2).

Check if the LVAL/DVAL/FVAL polarity settings match the camera timing (can be adjusted through LVALPolarity, DVALPolarity).

2. Trigger no response

Confirm that the trigger source is correctly connected (DI/encoder) and the voltage level meets the specifications (DI high level 3-24V, low level<0.8V).

Check if the source of the corresponding output channel in TriggerOutputTrigSrc is configured correctly.

Confirm that AVS_SrameGrabberStartAcquisition has been called, and the triggering function only takes effect after the collection starts.

Observe whether the corresponding event count (such as DI0EventCount) increases. If not, check the front-end signal and debounce settings.

3. Encoder direction is opposite

Swap the wiring between encoder A+and A - or B+and B -, or select CW/CCW reverse through Encoder Input. Mode.

4. The image is not synchronized after multi card synchronization

Check the synchronization cable connection sequence of all cards to ensure that the main card output is connected to the first slave card input and connected in series to subsequent slave cards.

Confirm that the MultiCardSync.Mode configuration for all cards is correct and that the trigger source signal for the main card is stable (if using the same external sensor).

Measure whether the synchronization signal on the main card CN4 is output (requires an oscilloscope). If not, check the main card configuration and trigger source.

5. Firmware update failed

Use the Firmware Update tool provided by ADLINK, select the correct. bin file, and after the update is complete, perform a cold start (completely power off and then power on), otherwise the new firmware will not take effect.

Key points of development environment and API calling

PCIe-CPL64V adopts a brand new AVS SDK (not compatible with the old version CPL64), supports Windows 10/11 64 bit,. NET Framework 4.8 or above, and VC++Redistributable 2015 or above. The programming process is as follows:

Call AVS_LetDeviceCount to enumerate devices.

AVSOpenDevice opens the specified card number and channel.

AVS_CameraLinkImportCamFile loads CAM files.

If a callback is used, the AVS-FrameGrabberSetcallback will register the frame ready callback; If using blocking, loop call AVS_SrameGrabberGetFrame.

AVS_SrameGrabberStartAcquisition starts the acquisition process (triggering logic takes effect at this time).

Process the image in the callback or main loop and return the buffer through AVS-FrameGrabberQueueBuffer.

Stop collecting and turn off the device.

Special note: GetFrame and callback modes cannot be mixed; Dynamic modification of trigger parameters must be performed after stopping the collection process; AVS_FrameGrabberSetBufferCount can adjust the number of buffers before startup (default: 4, maximum: 100). Increasing the buffer will help smooth burst frame traffic.

Selection and application suggestions

For a single Full configuration camera (80 bit, 85MHz), PCIe-CPL64V is an ideal choice with ample bandwidth margin.

If four Base cameras need to be synchronized, it can be achieved by combining four cards with multiple cards for synchronization. Each card controls one camera, which is suitable for parallel detection of multiple workstations.

The encoder trigger mode is suitable for equidistant acquisition in continuous motion, such as defect detection on the surface of a coil. Comparing Count and Interval need to be calculated to ensure uniform line spacing.

The anti-interference ability (± 7V common mode range) of isolating I/O and encoder inputs enables it to adapt to the motor frequency converter environment, but it is still recommended to use shielded twisted pair and single ended grounding.