ADLINK DAQ-2500 Series Multi Channel Analog Output Card

ADLINK PXI/DAQ/DAQe-2500 series multi-channel analog output data acquisition card

Introduction: The core position of incentive sources in testing and measurement and the design philosophy of the 2500 series

In automated testing systems, data acquisition (DAQ) devices are typically divided into two functional domains: "measurement" and "excitation". Most DAQ cards emphasize high-precision analog inputs, while analog output channels are often used as auxiliary functions (usually only 2 channels). However, in sensor simulation, actuator driving, power management IC testing, and closed-loop control algorithm verification, a multi-channel, high update rate, and phase synchronized analog excitation source is precisely needed.

The Linghua PXI/DAQ/DAQe-2500 series is designed based on this requirement. Its most distinctive feature is that it takes multi-channel analog output as the primary performance indicator, providing 12 bit analog outputs of 4 channels (2501) or 8 channels (2502), each of which can independently achieve an update rate of 1 MS/s, and all channels can be updated simultaneously - this means that users can generate complex waveforms with multiple synchronized channels, such as three-phase sine waves, multiple PWM control signals, or custom arbitrary waveform sequences.

At the same time, the series did not neglect the data acquisition function, integrating 14 bit, 400 kS/s analog inputs (with 4 or 8 channels), combined with 24 digital I/O channels and dual channel 16 bit timers/counters, to form a complete "excitation response" measurement closed-loop platform. This article will present a comprehensive technical portrait to readers from the perspectives of hardware architecture, synchronization mechanism, software support, and actual deployment.

Analog output channel: core architecture and fine control

2.1 Output Channel Configuration and Model Differences

PXI/DAQ/DAQe-2501: Provides 4 analog outputs.

PXI/DAQ/DAQe-2502: Provides 8 analog outputs.

In addition to the number of channels, there is also a difference in the size of the D/A FIFO between the two: the 2501 board carries 8k sampling points, while the 2502 has 16k sampling points to accommodate the data buffering requirements when more channels are output simultaneously. The remaining analog output parameters are completely consistent.

2.2 Resolution and update rate

Resolution: 12 bits, no missing codes.

Maximum update rate: 1 MS/s (independent for each channel). This means that when 8 channels are output simultaneously, the total data throughput can reach 8 MS/s, which is sufficient to generate sine waves up to 500 kHz (satisfying the Nyquist sampling theorem).

Pendulum rate: 20 V/μ s, establishment time of 3 μ s to ± 0.5 LSB accuracy, ensuring fast transient response.

2.3 Output Range and Reference Source Flexibility

This series adopts the Multiplying DAC (MDAC) architecture, which not only supports the traditional fixed range output range, but also allows independent channel by channel programming:

Fixed range: 0~10 V (unipolar), ± 10 V (bipolar).

External reference range: 0~AOEXTREF (unipolar), ± AOEXTREF (bipolar), where AOEXTREF is the external reference voltage provided by the user (introduced through analog input pins).

This design is extremely advantageous for applications that require dynamic adjustment of output amplitude (such as temperature compensation of sensor excitation signal amplitude) or synchronization with external precision voltage references. Each channel can independently choose between internal or external references, and the polarity (single/double) can also be independently configured, greatly enhancing flexibility.

2.4 Hardware level arbitrary waveform generation (HWAWG)

This is one of the most eye-catching features of the series. Traditional waveform output relies on CPU or DMA to update the D/A register point by point, which can consume a large amount of system resources at high update rates. The 2500 series uses onboard D/A FIFO and hardware timing engine to transfer pre generated waveform data (length limited only by system memory) from host memory to FIFO through scatter aggregate DMA, and then output them one by one controlled by onboard clock. The CPU only needs to fill in initial data, and subsequent updates are automatically completed by hardware, thereby minimizing CPU load while ensuring uninterrupted waveform. This mechanism is crucial for generating long-term continuous signals, such as noise spectra and fatigue test sequences.

2.5 Trigger and synchronous output

Analog output supports software triggering, external digital/analog triggering, and SSI bus triggering. The triggering modes include post triggering, delayed triggering, and repeated triggering, which facilitate close synchronization with other instruments or tested devices.

2.6 Output driver and protection

Drive capability: ± 5 mA, supporting capacitive loads up to 1500 pF.

Stability: It can work stably under any passive load.

Offset error: Typical ± 8 mV (gain error ± 0.04% at full scale), accuracy indicators meet most industrial excitation requirements.

Analog input: The auxiliary measurement function should not be underestimated