ADLINK PXIe-3987/3977/3937 Deployment and Debugging

ADLINK PXIe-3987/3977/3937 Series Embedded Controller Deployment and Debugging Complete Manual

In the PXI Express automated testing platform, the selection and configuration of embedded controllers directly affect the overall performance of the system. The PXle-3987/3977/3937 series controllers launched by ADLINK are based on the seventh generation Intel ®  Core ™ The processor provides a multi-level computing solution from dual core i3 to quad core i7, balancing cost and computing power. This article is aimed at system integration engineers, providing a complete technical practice guide from hardware selection differences, on-site installation specifications, BIOS deep optimization (including TPM 2.0 and Secure Boot), dual BIOS fault recovery, to PXI triggered I/O advanced programming, to help test systems quickly land and run stably for a long time.

Differences in Series Models and Key Selection Points

This series includes three controllers, with the core difference being the processor specifications and corresponding power/performance balance:

Model Processor Core/Thread Base Frequency/Turbo Typical Power Consumption (cTDP) Target Application

PXIe‑3987 Intel ®  Core ™  I7-7820EQ 4C/8T 3.0/3.7 GHz 45W/35W high-density data processing, multi-channel synchronous acquisition

PXIe‑3977 Intel ®  Core ™  I5-7440EQ 4C/4T 2.9/3.6 GHz 45W/35W Universal ATE Test, Medium Load Control

PXIe‑3937 Intel ®  Core ™  I3-7100E 2C/4T 2.9 GHz (no turbo) 35W Cost Sensitive Single Function Tester

The three products share the same PCB platform and I/O interface, all supporting dual channel DDR4 SODIMM (up to 32GB 2400MHz), configurable PCIe links (x16 x8 or x4 x4 x4 x4), and a maximum system throughput of 16GB/s. When selecting, it is necessary to consider the computational intensity of the testing task and the heat dissipation capacity of the chassis - the i7 model can achieve a+12V current of 8A under heavy load (see specification table), and the power supply margin of the backplane needs to be ensured.

Hardware installation and key component maintenance (general process)

2.1 Physical Installation of Controller

The installation steps for all models are consistent, and the key points are as follows:

Anti static preparation: It is necessary to operate on a grounded anti-static pad and wear a wristband.

Chassis slot: Only the system slot (Slot 1) of the PXIe chassis can be inserted, otherwise the backplane link cannot be recognized.

Locking operation: When pushing the red pull rod, ensure that the rear positioning pin is aligned with the guide rail hole to avoid connector misalignment and damage.

Tighten screws: The four screws on the panel need to be tightened with a screwdriver to ensure anti vibration performance (meeting 0.21 Grms operating vibration).

2.2 Storage Device (HDD/SSD) Replacement

Pre installed 2.5 "SATA 6Gb/s hard drive or SSD (with optional capacity of 500GB HDD or 240GB SSD).

When replacing, it is necessary to disassemble the controller, remove the five screws of the hard drive bracket, and then remove the fixing screws on both sides.

Important: Replacing a non ADLINK certified SSD may not guarantee wide temperature range (0-55 ℃) and anti vibration performance. It is recommended to choose an industrial grade SSD and manually set "SSD" in the BIOS under "Advanced" ->"Onboard Devices Configuration" ->"SATA Signal Setting" to optimize signal timing.

2.3 Battery replacement and CMOS clearing

CR2032 battery: When replacing, pay attention to the positive pole (+) facing upwards, first clip in the positive pole buckle and then press the negative pole.

CMOS Reset (SW1): When the system fails to start or the BIOS settings are chaotic, set SW1 to the "Clear" position and hold it for 5 seconds before resetting to restore the factory default. This operation will not clear the TPM key (if Secure Boot is enabled, additional processing is required).

Advanced Explanation of BIOS Settings (Based on the New Version Menu)

The new version of BIOS (Revision 1.1) has added TPM 2.0 configuration and Secure Boot options, while optimizing CPU power control parameters. The following is a detailed explanation of key configuration items.

3.1 Processor and Power Optimization (CPU Configuration)

Go to 【 Advanced 】 → 【 CPU Configuration 】:

Hyper Reading: i7 model supported, recommended to enable on Windows 10 and Linux; Real time systems (such as RTX) may suggest shutting down to enhance determinism.

Turbo Mode: When turned on, i7/i5 can reach the highest turbo frequency, but power consumption increases. If the chassis has poor heat dissipation, it can be turned off.

Configurable TDP Boot Mode: Added "Up" option (compared to the old version), allowing dynamic increase in power consumption limit, suitable for short-term burst computing; Usually kept as' nominal '.

C States: It is recommended to keep "Enabled" to save energy, but if minimum latency is required, Package C State restriction can be disabled.

3.2 Onboard Device Configuration

COM Control: RS ‑ 232/422/485 the third mock examination switching, which needs to be selected according to the instrument interface on the site. After modification, it needs to be restarted to take effect.

SATA Controller: enabled by default, can be temporarily disabled if using external USB boot.

SATA Signal Setting: It is necessary to choose "HDD" or "SSD" according to the actual storage medium, which affects the signal balance parameters.

3.3 TPM 2.0 and Secure Boot (New Important Features)

In [Advanced] → [TPM 2.0 Configuration]:

Security Device Support: Set to "Enable" to activate TPM.

SHA-256 PCR Bank: It is recommended to enable it to comply with the security requirements of Windows 11 and higher versions.

TPM2.0 UEFI Spec Version: If installing Windows 10, select "TCG_1_2" compatibility mode; If it is Windows 11, select "TCG_2".

Secure Boot (located in the [Security] menu): Before setting "Attempt Secure Boot" to "Enabled", it is necessary to ensure that the system has installed a UEFI boot OS (GPT partition), otherwise it will result in inability to boot. After activation, it can prevent unsigned driver loading and enhance industrial control security.

3.4 Detailed steps for switching boot mode (Legacy vs UEFI)

For old DOS or specific RTOS, it is necessary to switch to Legacy mode:

[Boot] → [Boot Configuration] → Boot Mode Select "Legacy".

[Boot] → [CSM] → Set CSM Support to "Enabled".

Set the OpROM execution strategy for Network, Storage, Video, and Other PCI Devices to 'Legacy only'.

Press F10 to save and exit.

To restore UEFI, simply select "UEFI" in Boot Mode Select and load the optimized default values (F9).

3.5 System Health Monitoring

In [Advanced] → [Hardware Health Configuration], real-time reading of:

PCIe switch environment temperature and core temperature

System+3.3V,+5V,+12V and battery voltage

This data is extremely useful for verifying the heat dissipation design of the chassis.

PXI triggers I/O programming library (detailed explanation of functional functions)

This series shares the same set of trigger APIs, located at X:  ADLINK  PXI Trigger IO  Include  pixtrigio. h. The following is a practical explanation of key functions.

4.1 Initialization and Resource Management

TRIG_Init(): Must be called first, returns ERR_CoError to indicate success.

TRIG_Close(): Called before the application exits to release interrupts and memory resources.

4.2 Software triggering and status reading

TRIG_SETSoftTrg (U8 Status): Generate TTL level (0 or 1), which can be output to the SMB port or backplane trigger line.

TRIG_Gets SoftTrg (U8 * Status): Read the current software trigger value (default low level).

4.3 Routing Configuration Function (Core)

TRIG_Trigger_Route(U32 source, U32 dest, U32 halfway)：

Parameter description:

Source: Signal source, optional PXI_TRIG_VAL_SMB (external input), PXI_TRIG_VAL_SOFT (software), PXI_TRIG_VAL_TRIG0~7 (backplane cable).

Dest: Destination, within the same range as above (excluding SOFT).

Halfway: Only when source=SOFT and dest=SMB, a trigger line needs to be specified as the intermediate node, and in other cases, it is set as PXI_TRIG_VALINONE.

Typical use case:

External trigger synchronous multi board: Route SMB input to backplane TRIG0 → source=SMB, dest=TRIG0, halfway=NONE.

Software triggers output to the backplane: source=SOFT, dest=TRIG1, halfway=NONE.

Software triggers output to SMB (intermediate required): source=SOFT, dest=SMB, halfway=TRIG2 (select any idle trigger line).

4.4 Routing Query and Clearing

TRIG_Trigger_Soute_Query(): Returns the current source/dest/halfway value for debugging purposes.

TRIG_Trigger_Clear(): Reset all routes to default state.

4.5 Driver version acquisition

TRIG_dDriverRevision() returns the major and minor version numbers for compatibility verification.

Dual BIOS automatic fault recovery mechanism

This series retains a dual BIOS design, including a main BIOS and a backup BIOS, managed by independent hardware monitors.

Working principle: During normal startup, the main BIOS boots. If the startup timeout is caused by upgrade interruption or verification failure, the monitor automatically switches to the backup BIOS and prompts "Backup BIOS deployed".

On site handling: When this prompt appears, the system can still work normally, but it is necessary to contact technical support as soon as possible to refresh the main BIOS. During the waiting period for recovery, it is recommended to save the current configuration (which can be done through the BIOS's' Save as User Defaults').

Preventive measures: When updating BIOS, be sure to ensure stable power supply and do not cut off power midway.

Driver Installation and Software Ecology (Windows 10 64 bit)

In addition to the built-in drivers in Windows 10, the following components must be manually installed (downloaded from the corresponding product page on the ADLINK official website):

Intel Chipset Driver

Intel Graphics Driver

Intel Ethernet/LAN Driver（I219 & I210）

Intel ME（Management Engine）Driver

Intel RST（Rapid Storage Technology）Driver

GPIB Driver (compatible with NI-488.2 API)

PXI Trigger I/O Driver (providing the above API library)

PXI Platform Services (for chassis identification and resource management)

Optional installation of MAPS Core software suite for advanced measurement automation applications. Suggested installation sequence: chipset → graphics card → network card → ME → RST → trigger driver → GPIB → platform service.

Environmental tolerance and power supply recommendations

Temperature: The working temperature under SSD configuration is 0-55 ℃, and the HDD configuration is 0-50 ℃. The internal air duct of the chassis needs to ensure this range.

Vibration: 0.21 Grms (5-500Hz) during operation, 2.46 Grms during non operation.

Power consumption: When overloaded (CPU+storage busy),+12V reaches 8A,+5V 2.8A,+3.3V 5A. If the total power supply capacity of the chassis is insufficient, it may trigger frequency reduction or power failure. It is recommended to reserve a 20% margin.

Safety compliance and waste disposal

The product complies with the EU RoHS and WEEE directives and must be recycled according to local electronic waste regulations after disposal.

California Proposition 65: Some materials contain lead, cadmium, etc., but only in very small amounts and do not affect normal industrial use.

Equipment maintenance is limited to authorized technicians only. Improper battery replacement poses a risk of explosion, and it is essential to use CR2032 of the same specifications.