ADLINK PXIe-3987 Installation and Configuration Programming Guide

ADLINK PXIe-3987 Embedded Controller: Hardware Installation, BIOS Configuration, and Trigger I/O Programming Practice Guide

In modern automated testing and data acquisition systems, the PXI Express platform plays a central role. ADLINK PXIe-3987 as a seventh generation Intel based device ®  Core ™  The 3U PXI Express embedded controller with i7 processor provides powerful computing power and rich I/O interfaces for complex testing and measurement applications. This article aims to provide a comprehensive operation guide for system integrators and test engineers on the PXIe-3987 controller, from hardware installation, key component replacement, BIOS optimization to advanced trigger I/O programming, to help engineers quickly deploy and solve technical problems encountered in practical applications.

Product Overview and Hardware Architecture

The ADLINK PXIe-3987 PXI Express embedded controller is designed specifically for high-performance hybrid testing systems, with its core competitiveness derived from Intel ®  Core ™  I7-7820EQ processor (3.0GHz, single core Turbo frequency up to 3.7GHz) and mobile Intel ®  QM175 chipset. This controller supports dual channel DDR4 SODIMM memory, with a maximum capacity of 32GB and a frequency support of 2400MHz, ensuring smoothness in multitasking and large data throughput.

In terms of PCIe link capability, PXIe-3987 provides a highly flexible configurable switching architecture that supports two link modes: four link configuration (x4 x4 x4 x4) and dual link configuration (x16 x8), with a maximum system throughput of up to 16GB/s (based on PCIe 3.0 specifications).

Core I/O interface layout

The front panel of the controller integrates rich I/O interfaces, with specific functions as shown in the table below:

Interface Type Quantity/Specification Function Description

DisplayPort supports dual independent displays with a maximum resolution of 3840x2160 @ 60Hz

USB 3.0 2-channel high-speed data transfer, backward compatible with USB 2.0

USB 2.0 4-way support for external USB devices and operating system installation and booting

Gigabit Ethernet 2-channel based on Intel I210/I219 controller, supporting WoL (Wake on LAN)

GPIB (IEEE488) 1-channel (Micro-D 25P) onboard GPIB controller, compatible with NI-488.2 driver, with a speed of 1.5MB/s

COM Port 1-channel (D-sub 9P) BIOS can be configured for RS-232/422/485 mode

Trigger I/O 1-channel (SMB) programmable trigger signal input/output, connected to PXI trigger bus

Note: If using a 32-bit operating system, the addressable memory space will be limited and it will not be possible to fully utilize more than 4GB of physical memory. It is recommended to deploy a 64 bit operating system (such as Windows 10 64 bit) to maximize performance.

Hardware installation and maintenance of key components

2.1 Controller installation process

When installing PXIe-3987 into the PXIe chassis (usually slot 1 system slot), standardized procedures should be followed to prevent damage to the backplane connectors:

Physical positioning: Remove the dust cover from the corresponding slot of the chassis, ensure that the upper and lower edges of the controller are aligned with the chassis rail, and smoothly push it in.

Locking mechanism: Press down on the red locking rod to fully engage the controller with the backplate. Pay attention to aligning the positioning pin at the back of the pull rod with the positioning hole on the chassis guide rail to ensure even force distribution on the connector.

Tightening: Use a screwdriver to lock the four fixing screws on the panel to ensure stable operation of the controller in a vibrating environment.

2.2 Storage Device (HDD/SSD) Replacement Guide

PXIe-3987 comes pre installed with a 2.5-inch SATA hard drive or solid-state drive (supporting SATA 6.0 Gb/s and AHCI mode). If you need to upgrade or replace, please follow the steps below:

Disconnect the power and unplug the controller from the chassis, placing it on an anti-static workbench.

Remove the five screws that secure the hard drive bracket and gently lift the bracket.

Remove the four screws that secure the hard drive on both sides of the bracket and take out the old hard drive.

Install a new hard drive (maximum supported capacity depends on market supply, interface standard is SATA 3.0) and perform reverse operation reset.

Reinsert the controller, power on to enter BIOS (press DEL key), and check the hard disk recognition status in 【 Advanced 】 ->【 Onboard Devices Configuration 】 ->【 SATA Configuration 】.

2.3 On board battery replacement and CMOS clearing

Battery replacement (CR2032): When the system time is abnormal or the BIOS settings cannot be saved, the battery needs to be replaced. Use a small flat head screwdriver to gently pry up the old battery from the negative buckle. When installing the new battery, make sure the positive pole (+) is facing upwards. First, insert the positive buckle, and then press the negative buckle to lock it in place.

CMOS reset: If the system cannot start due to overclocking or incorrect settings, the onboard SW1 switch can be used. Turn the switch from Normal to Clear and wait for 5 seconds before resetting to restore the BIOS to its factory default values.

BIOS Advanced Settings and Optimization (Based on AMI UEFI BIOS)

PXIe-3987 uses American Megatrends BIOS, and when starting up, press the "Delete" or "ESC" key to enter the settings interface.

3.1 System Information Monitoring

Under the [Main] menu, engineers can view key hardware status:

Link Cap: Display the current PCIe link configuration (x16 x8 or x4 x4 x4).

Processor Information: Displays CPU frequency, number of cores, and support for VMX/VT-d virtualization technology.

System Management: Provides SEMA firmware version, hardware version, and serial number for asset management.

3.2 Onboard Equipment Configuration (Key Steps)

Go to 【 Advanced 】 ->【 Onboard Devices Configuration 】:

COM Control: Switch the serial port to RS-232, RS-422, or RS-485 mode (default to RS-232 at the factory) according to fieldbus requirements.

SATA Signal Setting: If an SSD is installed, it is recommended to force it to SSD mode to optimize signal timing; If it is HDD, select HDD.

Hot Plug: If you need to replace the hard drive during system operation (supported by the chassis), you can enable the Hot Plug function on the corresponding SATA port.

3.3 Startup Mode and Compatibility (Legacy/UEFI)

For traditional DOS environments or specific real-time operating systems (RTOS), it may be necessary to switch to Legacy Boot mode. The operation path is as follows:

Go to [Boot] ->[Boot Configuration] and set Boot Mode Select to LEGACY.

Go to [Boot] ->[CSM Configuration] (Compatibility Support Module):

Set CSM Support to Enabled.

Set Network, Storage, Video, and Other PCI devices to Legacy respectively.

Press F10 to save and restart.

Note: When installing Windows 10 64 bit in UEFI mode, it is recommended to turn off CSM and ensure that the hard disk partition table is in GPT format to support secure boot.

PXI Trigger I/O Function Programming Reference (API Application)

The SMB trigger interface on the front panel of PXIe-3987 is crucial for synchronous multi board testing systems. This function is implemented through the PXI Trigger I/O driver library, and the API files are located in the Include folder of the driver installation directory.

4.1 Data Type Definition

Specific data types are defined in Pixrigio. h, such as U8 (8-bit unsigned characters) and U32 (32-bit unsigned integers). It is recommended to follow this specification when programming to ensure cross language compatibility (such as C/C++, Delphi).

4.2 Core Function Analysis

Initialization and shutdown

TRIG_Init(): Must be called first, used to initialize and trigger I/O hardware resources.

TRIG_Close(): Called before the application exits to free resources and prevent memory leakage.

Software triggering and acquisition

TRIG_SETSoftTrg (U8 Status): Generate TTL level signals (0 is low level, 1 is high level) on the SMB interface or backplane trigger bus through software instructions.

TRIG_Gets SoftTrg (U8 * Status): Read the current software trigger status (default startup is low level).

Trigger signal routing (key function)

TRIG_Trigger_Soute (U32 source, U32 dest, U32 halfway): This function is used to flexibly configure signal paths.

Source: Optional PXI_TRIG_VAL_SMB (external input), PXI_TRIG_VAL_SOFT (software generated), or PXI_TRIG_VAL_TRIG0~7 (backplane trigger line).

Dest: Optionally route the signal to the SMB interface or backplane trigger line.

Halfway: When Source is software triggered and Dest is SMB, this parameter needs to specify a trigger bus as the signal relay point, usually set to PXI_TRIG_VALんE.

Routing query and clearing:

TRIG_Trigger_Soute_Query() is used for debugging and reading the current routing path.

TRIG_Trigger_Clear() is used to reset all routing settings and restore the default state.

4.3 Typical application scenarios

Scenario: Use software to trigger the high-speed digitizer on the PXI backplane for data acquisition.

Implementation logic: Call TRI_SetSoftTrg (1) to generate a rising edge, and route PXI_TRIG_VAL_SOFT to PXI_TRIG_VAL_TRIG0 through TRIG_Trigger-Route. All slave devices on trigger line 0 will start collection synchronously.

Dual BIOS fault recovery mechanism

PXIe-3987 is equipped with Dual BIOS technology, which is a hardware level backup and recovery solution independent of the operating system:

Working mechanism: When the main BIOS starts, the independent monitoring controller will monitor the startup status in real time. If the main BIOS fails to boot due to firmware update or data corruption, the monitor will automatically activate the backup BIOS to boot the system.

On site response: When the prompt "Backup BIOS deployed" appears on the startup screen, it indicates that the backup BIOS has been automatically switched. At this point, the system can run normally, but the main BIOS data has been lost. It is recommended to enter the BIOS interface and press F9 to load the optimized default values before restoring the main BIOS, and confirm hardware stability.

Restore main BIOS: Contact ADLINK technical support for recovery tools, which typically require specific burning software to refresh the backup image to the main BIOS storage area.

Environmental tolerance and power supply considerations

6.1 Work environment boundaries

To ensure the accuracy of data collection, it is necessary to strictly follow the environmental specifications:

Temperature range: When equipped with SSD, the upper limit of operating temperature is 55 ℃; When equipped with HDD, the upper limit is reduced to 50 ℃ (mechanical hard drives are more sensitive to high temperatures).

Relative humidity: 5% to 95% (no condensation).

Vibration tolerance: It can withstand random vibrations of 5 to 500Hz and 0.21 Grms under operating conditions, suitable for vehicle mounted or production line ATE (automatic testing equipment) environments.

Design suggestion: When selecting the chassis, it is necessary to confirm that the fan air volume of the chassis is sufficient to cover the controller CPU heat sink, otherwise it may trigger CPU frequency down protection and affect test throughput.

6.2 Estimation of Power Consumption

The following are typical power consumption data for reference in selecting the system power module (PXIe backplane power supply capability):

Load status+3.3V+5V+12V

Typical idle (Win10 standby) 5A 2.5A 2A

Overload operation (CPU full load+storage read/write) 5A 2.8A 8A

Attention: When the+12V current demand suddenly increases under heavy load, it is necessary to ensure that the PXIe chassis backplane has sufficient current margin on this voltage rail.

Compliance and Safety Statement

Electromagnetic Compatibility (EMC): Compliant with EN 61326-1 Class A, FCC Part 15 Class A, and ICES-003 standards, suitable for industrial environments. If used in residential areas, it may cause radio frequency interference and additional filtering measures need to be taken.

Restriction of Hazardous Substances (RoHS): Fully compliant with the EU RoHS directive, products should be recycled according to local WEEE directives after disposal, and are prohibited from being discarded at will.

California Proposition 65 warns that some cables and solder in the product may contain chemicals such as lead and cadmium, and must be labeled under California law. But this only applies to regulatory compliance and does not affect the safety of industrial site use.