ADLINK PXIe-9529H Dynamic Signal Acquisition Configuration Guide

IEPE incentive: Each channel independently controls a current of 4 mA (24V compliance) and supports TEDS smart sensors (requires software analysis).

3.3 Input Range and Data Format

The module supports two fixed ranges of ± 1 V and ± 10 V, and the LSB (least significant bit) corresponding to the 24 bit ADC are 0.119 μ V and 1.19 μ V, respectively. The digital encoding adopts binary offset code (Midscale=x80000), with full scale corresponding to 0x7FFFFF and negative full scale corresponding to x80000. In actual programming, the driver API will automatically complete the conversion between voltage values and digital codes, and users do not need to manually calculate.

Detailed explanation of trigger source and trigger mode

4.1 Trigger Source Architecture

PXIe-9529H provides up to 7 trigger sources, which can be flexibly selected through software (as shown in the architecture diagram below):

Trigger source signal type minimum pulse width application scenario

Internal triggering in software triggered instant command N/A automated testing sequence

External digital triggers SMB front-end input, TTL 5V 20 ns external event synchronization (such as speed pulse)

PXI STAR star trigger, TTL 300 ns multi chassis synchronization (requires support from PXI backplane)

PXIe-DSTARB LVDS differential signal 300 ns high noise resistance and high-speed synchronization

PXI Trigger Bus [0:7] Backplane TTL Bus 300 ns Synchronization of Multiple Modules in the Same Chassis

Simulate triggering of arbitrary AI channel level detection with 24 bit resolution and conditional triggering based on signal amplitude

SSI bus system synchronous interface 8 ns multi module precision cascade (see next section)

4.2 Simulation triggering function (key features)

Simulated triggering is an important capability of the DSA module, and users can choose any channel from CH0 to CH7 as the monitoring source without the need for additional wiring. The triggering conditions include:

Positive slope trigger: The signal changes from below the trigger level to above the trigger level.

Negative slope trigger: The signal changes from above the trigger level to below the trigger level.

The trigger level can be set arbitrarily within the range with a 24 bit resolution (for example, at a range of ± 10 V, the voltage step is approximately 1.19 μ V).

Engineering application example: In impact response testing, the simulated trigger threshold can be set to 1.5 V (positive slope), and when the acceleration signal exceeds this value, the complete waveform recording of all channels will be activated.

4.3 Trigger mode (timing control)

Post Trigger: After the triggering event occurs, a fixed number of samples are collected. Suitable for recording the response process after triggering.

Delay Trigger: After the trigger occurs, the collection starts after a specified time delay (based on a 125 MHz time base, with a step of 8 ns and a maximum delay of about 34 seconds). It is suitable for systems that capture signals before triggering (expandable with pre trigger buffer).

Re Trigger: Under multiple triggering events, a fixed sample is collected each time, and all data is continuously stored in the FIFO. The minimum interval between two triggers is only one PCIe clock cycle (8 ns), suitable for high-speed burst measurement.

Multi Module Synchronization (SSI) and System Expansion

For high throughput applications such as 32 channel acoustic arrays, multiple PXIe-9529H modules need to be synchronized. This module utilizes the PXI Trigger Bus [0:7] of the PXI backplane as the system synchronization interface (SSI), without the need for external cables.

5.1 Synchronous Configuration Plan

Master module: receives external/software/analog triggers and routes the trigger signal to the PXI Trigger Bus (optional 0-7 wires). At the same time, the sampling clock of the main module can be locked to the 10 MHz reference of the backplane to ensure frequency consistency.

Slave module: configured to receive trigger signals from the same PXI Trigger Bus (as a digital trigger source), with the sampling clock also locked to 10 MHz on the backplane.

5.2 Key timing parameters

SSI_TRIG signal (trigger distribution): When used as output, it reflects the current acquisition trigger event; As an input, it serves as a trigger source for the slave module. Rising edge detection, minimum pulse width of 8 ns.

Unified time base: Each module supports the use of PXIe backplane 10 MHz as the PLL reference, ensuring the phase certainty of the multi module ADC sampling clock, which is crucial for sound source localization or beamforming applications.

Configuration process (software perspective):

Main module: Call API to select trigger source (such as external digital trigger), and call Trigger_Soute to map AD_TRIG signal to PXI_TRIG0.

Module: Call the API to set the trigger source to PXI_TRIG0 and select PXIeBackplan_10MHz as the time base source.

Start the main module to collect data and synchronize responses from all slave modules.

Automatic calibration and maintenance

6.1 Calibration constant storage mechanism

PXIe-9529H is equipped with a high-precision reference voltage source (measured and recorded at the factory) and provides two types of storage banks: