Honeywell IPC 620-06 Programmable Controller

Honeywell IPC 620-06 Programmable Controller

Introduction

In the development of industrial automation, the Honeywell IPC 620 series programmable logic controller (PLC) became one of the core control devices for factory automation in the late 1980s to mid-1990s due to its modular design, powerful communication capabilities, and high reliability. The IPC 620-066 processor system (model 620-0636) is a high-performance single slot processor in this series, supporting up to 192 I/O points, multiple communication options, and online programming functions. It is widely used in packaging, material handling, metal processing, and process control fields. This article is based on Honeywell's official "IPC 620 Programmable Controller Model IPC 620-06" technical manual (form number 620-8975), which fully restores the technical details of this classic PLC system from five dimensions: hardware architecture, system configuration, operating principles, instruction system, and diagnostic maintenance.

Hardware Architecture: Modularity and Scalability

2.1 Selection of Processor Rack and Chassis

The IPC 620-06 system uses a dedicated processor rack and offers four models to meet different installation requirements:

Model Name I/O Slot Number Characteristics

620-0090 standard full-size rack with 8 supports I/O expansion modules and option modules

620-0091 Enhanced full-size rack with 8 additional upper layer local buses, supporting dual bus communication (such as servo modules)

620-0092 standard half size rack 4 without expansion module and option module slots

620-0093 Enhanced Half Size Rack 4 with Upper Local Bus

All racks comply with the "HE" standard and can be installed in 19 inch cabinets or panels through reversible brackets. The connector adopts anti misalignment design to prevent module reverse insertion.

2.2 Processor Module (PM) 620-0636

The processor module is the core of the entire system, using Motorola 68B09E microprocessor, onboard 2K program memory (expandable), and includes the following key features:

Memory and registers: Output status table 768 bits (0-767), where 0-191 is the actual I/O output and 192-767 is the control relay; There are 256 addresses in the 16 bit register area, ranging from 4096 to 4351.

Battery backup: Built in AA type 3V lithium battery, supporting memory and register data retention for at least 6 months. The front of the module is equipped with a battery compartment and a "BATTERY PASS" indicator light. Attention: Lithium batteries are strictly prohibited from being air shipped, short circuited, overcharged, burned, or punctured.

EPROM extension: onboard U32 socket, supporting 27128 EPROM as a permanent backup for user programs. When powered on, the processor automatically copies the contents of the EPROM to RAM and determines whether to retain the output status table and register data based on the battery status.

DIP switch configuration: The processor interface board (SW1) and MPU board (SW1, SW2) have three sets of 8-bit DIP switches, which are used to set the forced function (FORCE), battery low voltage start suppression, online programming permission, output fault response, and processor rack I/O slot capacity (0/8/16/32 points). The specific setting method can be found in the appendix.

2.3 Power Supply Module (PSM)

The system supports multiple power modules, which are used for processor racks and I/O racks respectively:

Processor rack dedicated power supply (full-size)

620-0041:115/230VAC switchable, providing 8A@5VDC +600mA @ ± 15VDC, power consumption 95VA, surge 15A/cycle.

620-0083:115/230VAC toggle switch, provided 15A@5VDC +1.16A @ ± 15VDC, total output ≤ 90W, power consumption 110VA, surge 20A/cycle.

620-0046:24V DC input (20-28V), 8A@5VDC +600mA @ ± 15VDC, power consumption 96VA, surge 40A.

I/O rack/half size processor rack power supply

621‑9932：24VDC， 8A@5VDC +600mA @ ± 15VDC, single slot width.

621‑9933：115/230VAC， Double slot width, 10-- 15A@5VDC +1.3-2A @ ± 15VDC, the output characteristics are shown in the derating curve in Figure 4.

621‑9934：115/230VAC， 8A@5VDC +600mA @ ± 15VDC, single slot width.

All power modules are equipped with front-end replaceable fuses and 5VDC green LED indicator lights. 230VAC operation requires replacing the corresponding specification fuse and adjusting the voltage selection switch/short circuit board.

2.4 I/O System and Expansion

The IPC 620-06 adopts the 621 parallel I/O system, supporting 8, 16, and 32 point digital modules as well as various analog and special function modules. The I/O rack is divided into full-size (12 slots) and half size (6 slots), and is connected to the processor rack through the I/O expansion module (IOEM) 620-0053. The parallel link uses 50 core D-type cables, with a maximum total length limit of 50 feet. It adopts a daisy chain topology and can connect up to 2 I/O racks (achieving 192 point I/O).

The parallel I/O module (PIOM) 621-9937 is the interface and control core of the I/O rack, replacing the early model 621-9930. Each I/O rack must be equipped with a PIOM, which includes the following functions:

Decoding the address data sent by the processor to generate chip selection signals corresponding to the slot positions;

Manage output fault response (clear or hold);

Hardware configuration is completed through two sets of DIP switches (SW1 sets the starting address of the rack, and SW3-SW5 sets the capacity of each slot point).

2.5 Network and Communication Options

The processor rack slot M can install the following communication modules to achieve system level interconnection:

Control Network Module (CNM) 620-0038: High speed peer-to-peer communication, up to 8 nodes sharing I/O status, transmission medium is single pair twisted pair cable (4000 feet) or optional dual axis cable (8000 feet), network polling time ≤ 18ms.

Communication Interface Module (CIM): Supports Modbus RTU, Honeywell DMCS, ABC protocol, and is used for serial communication with 627 series products and other smart devices.

Hiway Interface Module (HIM): Connect Honeywell TDC-3000 data highway to achieve PLC and DCS integration.

Operator Panel Interface Module (OPI): Connect on-site buttons, keyboard displays, etc. through coaxial cables.

2.6 Programming and Monitoring Equipment

623-6000 Loader/Terminal: a dedicated programming terminal that supports ladder diagram editing, monitoring, document generation, and EPROM programming.

623-60 MS-DOS Loader: A personal computer programming software based on MS-DOS, compatible with L/T tape format, supporting symbol addressing and online programming.

627 LOS local operation station: an industrial grade MS-DOS AT compatible workstation that provides supervisory control and operator interface.

System configuration and address allocation

3.1 Processor Rack I/O Slot Configuration

The SW1 and SW2 on the MPU board of the processor module are used to define the I/O point capacity of slots A-H in the processor rack. Each slot corresponds to a set of "first setting/second setting" switches, configured according to the table:

Module type first setting second setting

0-point (empty) closure/ON closure/ON

Open/Close/ON at 8 o'clock

16 o'clock closing/ON opening/OFF

32 point disconnect/OFF disconnect/OFF

The factory defaults to setting all slots to 32 points. When configuring, the corresponding switch needs to be modified according to the actual installation module.

3.2 Parallel I/O Rack Address Allocation

The PIOM of each I/O rack is set to the rack starting address through SW1 (8-bit, binary weights 8/16/32/64/128/256/512/1024). Rule:

The slot A of the processor rack has a fixed starting address of 0.

The starting address of the first I/O rack is equal to the ending address of the processor rack plus 1.

The starting address of the subsequent I/O rack is equal to the ending address of the preceding rack plus 1.

The starting address of the last rack must not exceed 184.

Each I/O slot is configured with point capacity through PIOM's SW3, SW4, and SW5 according to the same switch table as the processor rack. Supports mixing 8, 16, and 32 point modules in the same rack, but must be set correctly for each slot.

3.3 Output fault response configuration

PIOM's SW2-1 determines that when an output module fault, cable disconnection, external power failure, or processor entering Program/Disable mode is detected, the output of this rack should be reset to zero (closed/ON) or remain in its final state (open/OFF). SW2-2 determines whether to recognize output module faults (closed/ON recognition, open/OFF ignored).

The processor module interface board SW1 can also configure the response of the processor rack output to faults.

Operation mode and program execution

4.1 Three operating modes

Front panel three position key switch selection system status:

Program mode: The processor only responds to commands from programming terminals or CIM, does not scan user programs, and does not update I/O. The output status is reset or maintained according to PIOM settings.

DISABLE mode: Execute user program, update output status table, but do not update actual physical output. Used for debugging and safety interlock testing.

RUN/PROGRAMME mode: When the key is in this position, it can be requested through software to switch between RUN and PROGRAMME sub modes. Under normal operating conditions, the processor is in RUN sub mode, performing scans and updating I/O.

Mode priority: RUN/PROJECT>DISABLE>PROGRAMME. CIM can place the processor in lower priority mode, but cannot elevate it to high priority mode; The programming terminal can request the Program mode and has the highest control authority.

4.2 Program scanning cycle

A complete scanning cycle includes:

Input Status Scan (ISS): Approximately 2ms, the processor sends a gate pulse to all input modules, locks the current input data, and checks for output module faults. The fault address is stored in the system status table.

User program execution: Solve the ladder diagram logic item by item, and update the output status table and physical output immediately when executing the output instructions.

End processing: When encountering EOM (End of Memory) instruction or user programmed "Return to Program Start" instruction, restart the next cycle.

If the Control Network Module (CNM) is installed, the scanning cycle will increase by approximately 4.2ms.

4.3 Parallel I/O Communication Mechanism

The processor broadcasts address data in parallel to all PIOMs through the I/O expansion module (IOEM).

PIOM decodes the address and generates the corresponding slot chip selection signal.

The input module locks the field signal and holds it in the input register when the chip selection is valid.

After the output instruction is solved, the processor simultaneously sends the raw data and the inverted data to the output module. The output module compares the two internally and sets the fault flag if there is a mismatch.

In the next round of ISS, the processor reads the fault flag and records the fault slot address.

This mechanism effectively detects I/O bus and module level hardware failures.

4.4 EPROM Operation and Memory Backup

When the processor module U32 socket is installed with 27128 EPROM, the system power on behavior is as follows:

Cold start (battery failure or first power on): EPROM user program, register data (4096-4351), and jump table (8192-8447) are overwritten to RAM; Clear the output status table to zero.

Hot start (battery normal): Only the EPROM user program is copied to RAM, and the output status table, registers, and jump table retain the values before power failure.

This design ensures that the accumulated value of the timer, the current value of the counter, and the hold type output are correctly restored after a brief power outage. Important: When using EPROM and permanently modifying the program, it is recommended to remove the battery for 1 minute before powering it on to force a cold start.

Instruction System and Programming Features

IPC 620-06 supports a complete ladder diagram instruction set, with instruction execution time quantified in microseconds. The main categories are as follows:

5.1 Relay Logic

Normally open/normally closed contacts, rising/falling edge trigger contacts, branching, output, hold output, latch/unlock.

5.2 Timer and Counter

0.1 second/1.0 second conduction delay, disconnection delay, and hold type conduction delay timer.

Up and down counter (counting range -65535~+65535).

5.3 Jump and Skip

Conditional skip (preserve output or force disable), jump, indirect jump, return to program start.

5.4 Sequencer

User data table storage (up to 1024 sets of 16 bit data), used to control repetitive actions or batch data storage.

5.5 Data Transmission and Arithmetic

Bring In/Send Out (16 bit I/O status or register data).

PUSH/PULL (batch transmission of multiple sets of 16 bit data).

Constant, indirect addressing.

Add, subtract, multiply, divide, compare (equal to, less than, greater than), zero detection.

5.6 Special Instructions

Input Status Scan (ISS): Users can force the insertion of a scan cycle.

Empty operation (NOP): facilitates online modification of programs.

Typical execution time: The basic contact is about 7.9-12.8 μ s, the timer is about 30-67 μ s, and the arithmetic instruction is about 72-511 μ s. The complete instruction execution schedule is shown in Table 7 of the manual.

5.7 Enhanced Run Mode Programming (ARMP)

The processor with firmware version ≥ 48 supports online program modification. The ARMP function allows adding, deleting, or editing ladder diagrams through programming terminals in RUN mode, with a maximum scan time increase of 20ms. Enabling conditions: processor in RUN/ROG, online programming enabled, watchdog timer set ≥ normal scan+20ms, programming terminal in MS-DOS 3.0 or higher, and terminal in Program mode. When ARMP is running, the system status table registers 2487-2488 display 0xAAAA, and when idle, they display 0x5555.

Diagnosis and maintenance

6.1 Self diagnostic system

Power on self-test: After the processor is reset, it automatically performs microprocessor register testing, firmware checksum, RAM read-write testing, user memory capacity detection, etc. If the RAM test fails, power off and remove the battery to clear the fault flag.

Program memory verification: The processor calculates the initial checksum of the user program during each reserved scan, and reads 24 words per scan cycle for cumulative verification during runtime. If the checksum does not match, stop scanning and place an error flag.

Online check: Verify weekly whether the first address is an ISS instruction, check the EOM position, and reset the watchdog timer (150-200ms timeout).

6.2 System Status Table

The memory address 2400-2500 area is reserved as a system state table to store critical diagnostic information, which can be read through PULL instructions or programming terminals. Common address:

Address Content

2413 Scan for lost/battery status

2415 output card fault count

2417-2431 addresses of the last 8 faulty modules

2291 Current scanning time

2295 forced I/O points

2302 processor firmware version (ARMP supported for 48 and above)

6.3 Fault Handling Strategy

Output module fault: If PIOM is set to recognize faults, the output of the rack will immediately reset (or remain) when the fault occurs, and the fault address will be stored in the status table.

Power failure: When the AC input is below 83V (115V range) or 166V (230V range) for more than 11.5ms (24VDC input is below 19V for more than 7ms), the power module broadcasts a power signal to all I/O racks, and each rack responds with the set output status.

Scan loss: After the watchdog timeout, the processor stops running and the RUN LED goes off.