ADLINK DAQ/PXI-2000 series synchronous acquisition card configuration and triggering

Application and Configuration of ADLINK DAQ/PXI-2000 Series Synchronous Multi functional Data Acquisition Card

In automated testing, biomedical signal acquisition, transient measurement, and ATE systems, high-precision, multi-channel synchronous sampling is often the core requirement. The ADLINK DAQ/PXI-2000 series is a high-performance multifunctional data acquisition card based on a 32-bit PCI architecture, providing 4-channel synchronous differential analog input, combined with programmable gain, flexible trigger mode, and bus master DMA (with Scatter/Trainer) capability, suitable for harsh scenarios such as automotive testing, cable inspection, laboratory automation, etc. This series includes four models: DAQ/PXI-2010 (14 bit/2MS/s), 2005 (16 bit/500kS/s), 2006 (16 bit/250kS/s), and 2016 (16 bit/800kS/s). It also provides 2 channels of 12 bit D/A output (1MS/s update rate), 24 programmable digital I/Os, two 16 bit general-purpose timers/counters, as well as a unique 8-bit synchronous digital input (2010 only) and system synchronization interface (SSI), supporting multi card cascade synchronization.

Overview of product series and core selection indicators

The DAQ/PXI-2000 series is positioned as a high-precision synchronous sampling card, with its biggest highlight being the 4-channel fully synchronized differential input, which avoids the phase delay between channels caused by multiplexer switching and is very suitable for applications such as multiphase power measurement, vibration analysis, and transient capture. The core differences are as follows:

Model Resolution Maximum Sampling Rate A/D FIFO Typical Application Scenarios

DAQ/PXI-2010 14 bit 2 MS/s 8K sample high-speed transient and intermediate frequency signal

DAQ/PXI-2016 16 bit 800 kS/s 512 sample high-precision medium speed acquisition

DAQ/PXI-2005 16 bit 500 kS/s 512 sample audio and vibration

DAQ/PXI-2006 16 bit 250 kS/s 512 sample low-power, slowly varying signal

All models support software programmable input ranges (bipolar ± 10V, ± 5V, ± 2.5V, ± 1.25V; unipolar 0~10V, 0~5V, 0~2.5V, 0~1.25V) and gains (x 1, x 2, x 4, x 8). Input impedance 1G Ω//100pF, overvoltage protection with power on ± 30V and power-off ± 15V, suitable for industrial sites. The typical value of system noise is between 0.6 and 2.2 LSB rms (depending on the model and range), and CMRR can reach 85~97dB in the DC~60Hz range, effectively suppressing common mode interference.

The analog output section provides a 2-channel 12 bit DAC (LTC7545 or equivalent) with a maximum update rate of 1MS/s. The output range is bipolar ± 10V or unipolar 0-10V (supports external reference), with an output impedance of 0.3 Ω and a driving current of ± 5mA. It defaults to 0V steady state when powered on. Digital I/O based on 82C55A, 24 line programmable direction, TTL/CMOS compatible. In addition, the 2010 model provides an additional 8 synchronous digital inputs (SDI), which are synchronously latched with analog signals and suitable for mixed signal acquisition.

Key points of hardware installation and signal connection engineering

2.1 Unpacking and Anti static Treatment

The board is a static sensitive device, so it is necessary to operate it on a grounded anti-static pad and wear an anti-static wristband. Check that the packaging includes the board, All in One CD, and software installation guide. If damaged, do not power on.

2.2 PCI/PXI Plug and Play Configuration

The board follows the PCI plug and play specification, and the system BIOS automatically assigns IRQ and I/O addresses without the need for jumper settings. If there is an abnormal startup or unstable operation, it is mostly due to interrupt conflicts. You can check the BIOS settings or try replacing the PCI slot. The PXI version allocates resources through the PXI backplane.

2.3 68 pin VHDCI connector and signal definition

All external signals are connected through a 68 pin VHDCI female socket (AMP-787254-1), and key signals include:

Analog inputs: CHO+~CH3+, CHO -~CH3- (differential pair), reference AIGND;

Analog output: DA0OUT, DA1OUT, refer to AOGND; AOEXTREF is used for external reference;

Trigger signals: EXTATRIG (external analog trigger), EXTDTRIG (AI digital trigger), EXTWFTRIG (AO waveform trigger);

Timer/Counter: SRC, GATE, OUT, UPDOWN for GPTC0/1;

Assistive function input: AFI0 (can be used as external ADCONV or SCAN.START), AFI1 (external DAWR);

The SSI interface (only available in PCI version through 20 pin header) is used for multi card synchronization.

2.4 Analog Input Connection Strategy

Grounding reference signal source (such as non isolated instrument output): It is recommended to use differential connection to connect the signal source ground to AIGND, with the positive terminal connected to CHx+and the negative terminal connected to CHx -, utilizing the common mode rejection capability of the instrumentation amplifier.

Floating ground signal source (such as thermocouple, transformer output): A bias resistor (about 100 times the source impedance) needs to be added between the negative input terminal and AIGND to provide a DC bias circuit; If the source impedance is lower than 100 Ω, the negative terminal can be directly shorted to AIGND.

Although single ended connection is simple, it has poor noise resistance and is only recommended for use when the number of channels is limited and signal quality requirements are not high.

Analog Input (A/D) Operation Theory and Trigger Mode

3.1 Sampling timing and scanning concept

Although DAQ/PXI-2000 is a synchronous sampling card (producing 4-channel samples in a single conversion), its internal logic follows a scan based design and still uses "scan" as the sampling unit. The sampling interval is controlled by SI_comounter (24 bits): Scan Interval=SI_comounter/TIMEBASE (default 40MHz internal clock or external 1-40MHz clock). For example, when SI_comounter=160, the sampling interval=160/40M=4 μ s (i.e. 250kS/s). For 2010, the minimum SI_comounter is 20 (2MS/s); In 2005, it was 80; In 2006, it was 160; In 2016, it was 50.

3.2 Detailed explanation of four triggering modes

The board provides software triggering, external digital triggering, external analog triggering, and SSI triggering, in conjunction with four acquisition modes:

Post trigger: The most commonly used mode is to collect a specified amount of scan data (PSC_comounter) after the triggering event occurs.

Pre trigger: Continuously collect data before triggering, and only retain the most recent M scan data after triggering (M is set by the M-counter). The 'enable' bit can control whether to wait for M scans before triggering, ensuring a sufficient amount of pre triggered data.

Middle trigger: Save a specified number of scans (before+after) before and after the trigger, suitable for scenes where the waveform before and after the event needs to be observed.

Delay trigger: After triggering an event, a specified time (controlled by Delay_counter, unit can be TIMEBASE or sampling clock cycle) is delayed before starting data collection. It is suitable for avoiding transient interference at the moment of triggering.

In addition, it supports Re trigger mode. In Post or Delay mode, PSC_comounter scans are collected after each trigger, waiting for the next trigger until the specified number of re triggers is reached.

3.3 Data Migration: Scatter/Gather DMA

The onboard A/D FIFO (8K for 2010, 512 samples for the rest), combined with the bus master DMA of the PLX IOP-480 PCI controller, can directly transfer data to the host memory with minimal CPU intervention. The Scatter/Gather feature allows linking discontinuous physical memory blocks into linked lists, supporting unlimited capacity collection and avoiding difficulties in allocating large contiguous memory blocks. The software driver automatically manages the descriptor chain, and users only need to set the sampling number and buffer.

3.4 Synchronous Digital Input (2010 only)

After the A/D conversion is completed, each channel of this model additionally latches 2 digital inputs (SDI<1:0>_X, a total of 8 lines), which are combined with 14 bit analog data to form a 16 bit word (the lower 2 bits are SDI). In terms of sampling timing, digital signals are latched within 220-400ns after conversion, which is basically synchronized with analog signals and suitable for applications that require simultaneous recording of digital states (such as trigger flags and encoders).

Analog output (D/A) and waveform generation

4.1 Software updates and timed waveform generation

Software update: Directly write to DAC register, suitable for static output or low-frequency control.

Timed waveform generation: Generate continuous or finite waveforms through internal counters (UI_comounter sets the update interval, UC_comounter sets the number of points per waveform, IC_comounter sets the number of iterations). The highest update rate is 1MS/s (UI_comounter ≥ 40, using a 40MHz internal clock).

4.2 Trigger and Iterative Output

Supports Post trigger, Delay trigger, and Re trigger, similar to A/D. The iterative function allows for repeated output of single waveform data (limited or unlimited). If the number of waveform points is less than the FIFO size (2K for 2010 and 512 for others), there is no need to repeatedly load data from the host, greatly saving PCI bandwidth. DLY2_comounter can set the interval between two iterations to generate complex waveforms such as pulse trains.

4.3 Stop Mode

When the software stops waveform generation, you can choose:

Mode I: Stop immediately;

Mode II: Stop after completing the current complete waveform (UC_comounter points);

Mode III: Stop after completing the current iteration cycle (IC_comounter complete waveforms).

These three modes enhance the controllability of waveform output and are suitable for different real-time requirements.

Universal Timer/Counter and Auxiliary Functions

The board provides two 16 bit independent timers/counters (GPTC0/1), supporting 8 working modes, including:

Simple Gate Control Event Counting (Mode 1)

Single cycle measurement (Mode 2)

Pulse Width Measurement (Mode 3)

Single pulse/trigger pulse/continuous pulse generation (Mode 4-8)

Each counter has an external clock input (up to 10MHz), gate control, and direction control, and the output can be used for external device synchronization or triggering other functions. These modes provide hardware level solutions for speed measurement, pulse counting, PWM generation, and more.

Assistive Function Input (AFI) provides strong flexibility:

EXTTIMEBASE: Replace the internal 40MHz clock for custom sampling rates (1-40MHz).

AFI [0] can be configured as an external ADCONV (directly controlling A/D conversion) or an external SCAN_START, suitable for external event triggered sampling.

AFI [1] can be configured as an external DAWR (directly controlling D/A updates).

EXTDTRIG/EXTWFTRIG: External digital trigger inputs for AI and AO, respectively.

The System Synchronization Interface (SSI) supports multi card cascading (PCI version via 20 pin ribbon cable, PXI version via backplane trigger cable). Users can specify the internal timing signals of any card (TIMEBASE, ADCONV, SCAN_START, AD_TRIG, DA_TRIG, DAWR) as the master output, and other cards as slave receivers to achieve multi card synchronous sampling or waveform output, which is particularly suitable for multi-channel expansion (such as 4-card synchronous implementation of 16 channels).

Detailed explanation of trigger source and simulated trigger

In addition to software triggering and external digital triggering (edge detection), analog triggering is a major feature of this card. The analog trigger circuit can select the EXTATRIG pin (external analog input, range ± 10V, resolution about 78mV) or the selected ADC input channel (within full range, 8-bit resolution) as the source. 5 triggering conditions:

Below Low: Triggered when the signal falls below a low threshold.

Above High: Triggered when the signal exceeds a high threshold.

Inside Region: Triggered when the signal is between high and low thresholds.

High Hysteresis: Triggered when rising above a high threshold, while a low threshold determines hysteresis.

Low Hysteresis: Triggered when the drop crosses a low threshold, while a high threshold determines hysteresis.

These conditions are implemented through two thresholds and software configuration, which can effectively prevent false triggering caused by noise. The simulated triggering bandwidth is about 400kHz, suitable for automatic triggering scenarios that depend on signal levels.

Calibration and maintenance

The board is equipped with a precision reference source (5.000V, temperature drift ± 2ppm/° C, long-term stability 6ppm/1000Hr). At the factory, the calibration constant is written into the default area of the EEPROM, and three user modifiable areas are provided. It is recommended to perform automatic calibration (without external equipment) after preheating the installation environment for 15 minutes, and the software will automatically measure and correct offset and gain errors. After calibration, the new constant can be stored in any user area and labeled with a date/temperature for quick recovery under different environmental conditions.

Typical accuracy before and after calibration:

Offset error: ≤± 60mV before calibration, ≤± 1mV after calibration;

Gain error: ≤± 0.1% after calibration in 2010, and ≤± 0.03% in 2005/2006/2016.

Attention: All external connection cables must be removed before automatic calibration, as the D/A output may change during the calibration process.

Software Support and Rapid Development

ADLINK provides a multi-level software stack:

D2K-DASK: A DLL library for Windows 98/NT/2000/XP, supporting VB/VC+/Delphi/BC5, etc., with binary compatibility.

D2K-DASK/X: Linux shared library, supporting GNU C/C++.

DAQ-LabVIEW PnP: LabVIEW VI library, provided for free.

D2K-OCX: ActiveX control, easy to quickly build interfaces.

DAQBench (Business Edition): A complete collection of ActiveX controls, including data display and analysis.

All drivers and sample code are included in the accompanying CD, and a two-hour trial mode is provided (some software requires a license). Developers can easily configure channels, gains, trigger modes, and DMA buffers through APIs without worrying about underlying register operations.