ADLINK PCIe-7256 Industrial I/O Card Interruption and Relay

Interrupt handling: After the CPU responds to the IRQ, it reads the COS Latch register to obtain the changed input value and executes the corresponding logic (such as alarm, status update, actuator linkage).

Clear Interrupt: Write 1 to the COS_CLR bit of Interrupt Control Register (Base+0x08) to clear the interrupt request and automatically reset the COS Latch register, allowing the next change to continue triggering.

Note that COS Latch data only remains valid until the interrupt is cleared, and automatically resets to zero after clearing. Therefore, the service routine must complete data reading before clearing the interrupt.

Dual interrupt source mode: Channel 0/1 rising edge trigger

In addition to COS mode, PCIe-7256 also supports rising edge interrupts based on DI channel 0 and/or channel 1 (mode 2). In this mode, interrupts are only generated when the input signal jumps from low to high, making it suitable for capturing positive edge pulses (such as encoder zero position signals or start commands). Two interrupt sources can be enabled separately or simultaneously, and the interrupt sources are distinguished by the interrupt status register (Base+0x08, read).

Important constraint: COS mode and channel 0/1 rising edge mode share the same interrupt signal line and cannot be enabled simultaneously. If the corresponding enable bits are set simultaneously, the hardware will enter an undefined state (clearly marked as "Forbidden" in the manual). Therefore, when programming, it is necessary to ensure:

If COS is enabled (Bit8=1), Bit9 and Bit10 must be 0.

If Ch0 (Bit9=1) or Ch1 (Bit10=1) is enabled, Bit8 must be 0.

The read and write properties of the interrupt control register (Base+0x08) are different: write operations are used to enable/clear interrupts, while read operations are used to query interrupt and enable states. The clear operation is completed by writing "1" to the corresponding clear bit (Bit0~Bit2), which will not affect the enable configuration.

Key points of register mapping and low-level programming

All registers of PCIe-7256 are 16 bits wide and must be accessed using 16 bit I/O instructions. The base address is automatically assigned by the PCIe plug and play system and does not require manual setting. The register mapping is shown in the following table (offset address relative to Base):

Offset address write operation read operation

0x00 relay output CHO~7 control undefined (not supported)

0x02 Relay output CH8~15 Control relay output status feedback (CHO~15)

0x04 undefined isolated digital input status (CHO~15)

0x06 COS Setup Register COS Latch Register

0x08 Interrupt Control Register Interrupt Status Register

Relay control coding details

Each latch relay is determined by two control bits (S and R):

SET (1,0): The normally open (NO) contact is closed, the normally closed (NC) contact is open, and the corresponding output state is "1".

RESET (0,1): NO is open, NC is closed, and the corresponding output state is "0".

Prohibition of (1,1) or (0,0): The former may lead to uncertain states, while the latter has no effect and should be avoided.

Therefore, in actual programming, the 16 bit output data needs to be mapped into a 32-bit control word, with the high bit being the SET bit and the low bit being the RESET bit. But the official library function _7256-DO simplifies this process by simply passing in 16 bit data (bit=1 represents SET, bit=0 represents RESET), and the library automatically converts it into a dual coil pulse sequence. However, if performing direct operations on the underlying registers, it is necessary to follow the two bit encoding rule.

Difference between input register and read back register

Isolation input register (Base+0x04): reflects the actual level of the current DI pin (after optocoupler and filtering), updated in real time.

COS Latch register (Base+0x06): an input snapshot that freezes only when a COS interrupt is triggered, used to confirm the state at the time of the interrupt.

Relay read back register (Base+0x02): reads the actual state of the current relay contact (SET=1, RESET=0), which is consistent with the written value (unless there is a mechanical fault).

Board ID and Multi Card Management

When multiple PCIe-7256 are installed in the same system, assign a unique Board ID (0-15) to each card through the S1 DIP switch (4 bits). This ID is not related to the base address, but serves as a logical handle when calling library functions, ensuring that the software can accurately address specific cards. Set the rules as shown in Table 2-1 (binary encoding, 1=ON, 0=OFF), for example, ID=0 corresponds to all switches being OFF, and ID=15 corresponds to all switches being ON. The initialization function _7256Initialize will automatically detect all cards and return the number of cards that exist, and subsequent functions will be distinguished by the boardID parameter.

Software Drivers and Development Suggestions

ADLINK provides the PCIS-DASK SDK (supporting Windows 7/8.1), which encapsulates all underlying register operations, including DLLs and C/C++libraries. Appendix A lists the main functions: