ADLINK PXI-2020/2022 Synchronous Acquisition Card Configuration and Synchronization Guide

Important reminder: pins 2, 5, 8, 11, 14, 17, 20, 23, 36, 39, 42, 45, 48, 51, 54, and 57 of PXI-2020 are NC (unconnected), while PXI-2022 connects AIH8~15 and AIL8~15 channels on these pins.

Analog Input Operation Theory and Timing Control

3.1 Basic acquisition timing sequence

The acquisition engine of PXI-2020/2022 is based on three core counters (all 32-bit):

ScanIntrv (scan interval counter): determines the sampling rate, the formula is sampling rate=TIMEBASE/ScanIntrv. The internal time base is 80 MHz, therefore achieving 250 kS/s at ScanIntrv=320 and 125 kS/s at ScanIntrv=640. The effective range is 4-2 ^ 32-1, with a minimum value of 4 (corresponding to 20 MS/s, but limited by the maximum sampling rate of the ADC).

DataCnt: Specify the total amount of data collected in a single trigger, with a maximum of 2 ^ 31-1.

TribDelayTicks: Specify the delay time between the triggering event and the start of collection, measured in time base cycles (12.5 ns).

Acquisition process (triggered later as an example): After the triggering conditions are met, the acquisition engine generates a sampling signal based on the ScanIntrv value at each rising edge of the time base. The ADC converts the data and stores it in the onboard FIFO (16K samples x 32 bits). When the specified number of DataCnt is reached, the acquisition ends, and then the data is transferred from the onboard FIFO to the host memory through the main line control DMA.

3.2 Time base source selection and external clock

PXI-2020/2022 supports six time base sources, with priority configured by software:

Onboard 80 MHz internal oscillator (accuracy ± 25 ppm)

Front panel AFI [0.. 7] external input

Front panel SMB CLK IN (50 Ω AC coupling, 1-2 Vpp, 1-20 MHz)

PXI Star Trigger (PXI_STAR)

PXI triggers bus line 0 (PXI_TRIG [0])

PXI Backplane 10 MHz Clock (PXI10M)

The external time base input must be a TTL compatible continuous clock with a frequency range of 1-20 MHz (via AFI input) or 1-20 MHz (via SMB CLK IN). Attention: The external clock needs to be continuously stable, otherwise ADC conversion will encounter abnormalities.

3.3 Data Format

All models use 16 bit direct binary encoding. Under the bipolar ± 10V range, FSR-1 LSB corresponds to the code 0xFFFF (9.999695V), zero level corresponds to 0x8000 (0V), - FSR corresponds to 0x0000 (-10V), and LSB=305.2 μ V. Under the bipolar ± 2.5V range, LSB=76.3 μV。

Trigger system and acquisition mode

4.1 Trigger Source Architecture

PXI-2020/2022 provides five trigger sources (Figure 4-6):

Software trigger: directly triggered through function calls, suitable for single point or low-speed data collection.

External digital trigger: TTL edge signal input via SMB TRG IO or AFI [0.. 7], programmable polarity, minimum pulse width of 12.5 ns.

PXI star trigger: receives precise trigger signals from the timing slots of the PXI system, with slot to slot skew<5 ns, suitable for multi module synchronization.

PXI trigger bus [5]: Receive or send trigger signals through the backplane trigger bus to achieve communication between modules.

AFI auxiliary input: 8-channel multifunctional I/O (AFI0~AFI7), configurable as trigger input, time base input, or GPTC signal.

In addition, the board can output internal trigger signals through the SMB TRG IO, AFI0, or PXI trigger bus [5] for controlling external devices or other boards.

4.2 Detailed explanation of four triggering modes

Post trigger: The most commonly used mode is to start collecting a specified amount of data after triggering an event.

Pre trigger: Continuously collect data before triggering, and only retain the most recent M data after triggering. If the trigger occurs before M data collections are completed, the trigger signal will be ignored until M data collections are completed (M-enable mechanism), ensuring the completeness of the pre trigger data volume.

Middle trigger: Save a specified amount of data before and after triggering (M before+N after), suitable for scenarios where the waveform before and after the event needs to be observed. Also supports the M-enable mechanism.

Delay trigger: After triggering, the collection is delayed for a specified time (controlled by a 32-bit trigDelayTicks counter, unit=time base period, maximum delay ≈ 53.7 seconds @ 80MHz) before starting. It is suitable for avoiding transient interference at the moment of triggering.

4.3 Repeated triggering of collection

The ReTrgCnt counter (32-bit) can be used to configure a repeat trigger mode. In Post or Delay mode, DataCnt data is collected after each trigger, and then automatically enters a waiting state, waiting for the next trigger signal until the specified number of repeat triggers is reached. This feature is suitable for applications that require segmented collection of multiple events, and the triggering interval is extremely short (depending only on hardware response time).

Multi module synchronization - PXI trigger bus and SSI

PXI-2020/2022 utilizes the trigger bus (PXI_TRIG [0.. 7]) of the PXI backplane to implement the system synchronization interface (SSI), supporting multi card cascade synchronization in master-slave mode. Three core SSI signals can be flexibly routed to the PXI trigger bus: