ADLINK PXIe-3987 Installation and Configuration Programming Guide

BIOS Advanced Settings and Optimization (Based on AMI UEFI BIOS)

PXIe-3987 uses American Megatrends BIOS, and when starting up, press the "Delete" or "ESC" key to enter the settings interface.

3.1 System Information Monitoring

Under the [Main] menu, engineers can view key hardware status:

Link Cap: Display the current PCIe link configuration (x16 x8 or x4 x4 x4).

Processor Information: Displays CPU frequency, number of cores, and support for VMX/VT-d virtualization technology.

System Management: Provides SEMA firmware version, hardware version, and serial number for asset management.

3.2 Onboard Equipment Configuration (Key Steps)

Go to 【 Advanced 】 ->【 Onboard Devices Configuration 】:

COM Control: Switch the serial port to RS-232, RS-422, or RS-485 mode (default to RS-232 at the factory) according to fieldbus requirements.

SATA Signal Setting: If an SSD is installed, it is recommended to force it to SSD mode to optimize signal timing; If it is HDD, select HDD.

Hot Plug: If you need to replace the hard drive during system operation (supported by the chassis), you can enable the Hot Plug function on the corresponding SATA port.

3.3 Startup Mode and Compatibility (Legacy/UEFI)

For traditional DOS environments or specific real-time operating systems (RTOS), it may be necessary to switch to Legacy Boot mode. The operation path is as follows:

Go to [Boot] ->[Boot Configuration] and set Boot Mode Select to LEGACY.

Go to [Boot] ->[CSM Configuration] (Compatibility Support Module):

Set CSM Support to Enabled.

Set Network, Storage, Video, and Other PCI devices to Legacy respectively.

Press F10 to save and restart.

Note: When installing Windows 10 64 bit in UEFI mode, it is recommended to turn off CSM and ensure that the hard disk partition table is in GPT format to support secure boot.

PXI Trigger I/O Function Programming Reference (API Application)

The SMB trigger interface on the front panel of PXIe-3987 is crucial for synchronous multi board testing systems. This function is implemented through the PXI Trigger I/O driver library, and the API files are located in the Include folder of the driver installation directory.

4.1 Data Type Definition

Specific data types are defined in Pixrigio. h, such as U8 (8-bit unsigned characters) and U32 (32-bit unsigned integers). It is recommended to follow this specification when programming to ensure cross language compatibility (such as C/C++, Delphi).

4.2 Core Function Analysis

Initialization and shutdown

TRIG_Init(): Must be called first, used to initialize and trigger I/O hardware resources.

TRIG_Close(): Called before the application exits to free resources and prevent memory leakage.

Software triggering and acquisition

TRIG_SETSoftTrg (U8 Status): Generate TTL level signals (0 is low level, 1 is high level) on the SMB interface or backplane trigger bus through software instructions.

TRIG_Gets SoftTrg (U8 * Status): Read the current software trigger status (default startup is low level).

Trigger signal routing (key function)

TRIG_Trigger_Soute (U32 source, U32 dest, U32 halfway): This function is used to flexibly configure signal paths.

Source: Optional PXI_TRIG_VAL_SMB (external input), PXI_TRIG_VAL_SOFT (software generated), or PXI_TRIG_VAL_TRIG0~7 (backplane trigger line).

Dest: Optionally route the signal to the SMB interface or backplane trigger line.

Halfway: When Source is software triggered and Dest is SMB, this parameter needs to specify a trigger bus as the signal relay point, usually set to PXI_TRIG_VALんE.

Routing query and clearing:

TRIG_Trigger_Soute_Query() is used for debugging and reading the current routing path.

TRIG_Trigger_Clear() is used to reset all routing settings and restore the default state.

4.3 Typical application scenarios

Scenario: Use software to trigger the high-speed digitizer on the PXI backplane for data acquisition.

Implementation logic: Call TRI_SetSoftTrg (1) to generate a rising edge, and route PXI_TRIG_VAL_SOFT to PXI_TRIG_VAL_TRIG0 through TRIG_Trigger-Route. All slave devices on trigger line 0 will start collection synchronously.

Dual BIOS fault recovery mechanism

PXIe-3987 is equipped with Dual BIOS technology, which is a hardware level backup and recovery solution independent of the operating system:

Working mechanism: When the main BIOS starts, the independent monitoring controller will monitor the startup status in real time. If the main BIOS fails to boot due to firmware update or data corruption, the monitor will automatically activate the backup BIOS to boot the system.

On site response: When the prompt "Backup BIOS deployed" appears on the startup screen, it indicates that the backup BIOS has been automatically switched. At this point, the system can run normally, but the main BIOS data has been lost. It is recommended to enter the BIOS interface and press F9 to load the optimized default values before restoring the main BIOS, and confirm hardware stability.

Restore main BIOS: Contact ADLINK technical support for recovery tools, which typically require specific burning software to refresh the backup image to the main BIOS storage area.

Environmental tolerance and power supply considerations