ADLINK PXIe-9834 High Speed Digitizer Configuration Guide

ADLINK PXIe-9834 high-speed digitizer: detailed explanation of architecture, triggering, and multi module synchronization technology

In cutting-edge testing fields such as high-energy physics experiments, radar signal capture, fiber optic sensing, and partial discharge monitoring, strict requirements have been put forward for the sampling rate, bandwidth, dynamic range, and multi-channel synchronization of data acquisition systems. ADLINK PXIe-9834 is a 4-channel 16 bit 80 MS/s PXI Express high-speed digitizer that provides a complete solution for high-speed transient signal capture with up to 40 MHz analog bandwidth, flexible input impedance (50 Ω/1M Ω software optional), multi range (± 0.5V to ± 10V), and 1 GB onboard memory. This article is aimed at test system architects and hardware engineers, detailing the engineering deployment and optimization strategies of the module from dimensions such as module installation, front-end configuration (impedance/coupling/range), trigger source and trigger mode (including pre trigger, medium trigger, and re trigger), multi module synchronization (based on PXI backplane trigger bus and star trigger), external clock and reference clock, DMA data stream, and automatic calibration, to help build a high-frequency high-precision acquisition system.

Product positioning and core specifications

PXIe-9834 is a 3U single slot PXI Express digitizer designed specifically for transient signal measurements that require high sampling rates and wide bandwidth. Its core features include:

Sampling rate and resolution: up to 80 MS/s synchronous sampling per channel, 16 bit successive approximation ADC, no inter channel phase delay.

Analog input: 4-channel single ended SMA interface, input impedance 50 Ω or 1M Ω software switchable, coupling mode DC or AC (software select).

Range: ± 0.5V, ± 1V, ± 5V, ± 10V (± 10V is only available in 1M Ω impedance mode).

Bandwidth and filtering: -3 dB bandwidth, typical 40 MHz, built-in 10 MHz/20 MHz digital filter (software optional).

Onboard memory: 1 GB (based on DDR3), supports long-term continuous acquisition, even when running at the highest sampling rate.

Bus interface: PCI Express Gen1 x4, supports Scatter Gather DMA, with a theoretical continuous transfer rate of approximately 640 MB/s (four channels 80 MS/s x 2 bytes=640 MB/s).

Trigger: software trigger, external digital trigger (SMA, TTL), analog trigger (any AI channel) PXI Trigger Bus[0..7]、PXI STAR、PXIe_DSTARB。

Trigger modes: post trigger, delayed trigger, pre trigger, medium trigger, and re trigger (can be triggered repeatedly in post trigger/delayed trigger modes).

Clock: Internal 80 MHz oscillator (accuracy ± 25 ppm), external sampling clock (10~80 MHz, via CLK IN), external reference clock (10 MHz, via CLK IN or PXI backplane 10 MHz).

Calibration: Fully automatic calibration, built-in reference source (1.8V/0.9V/0.45V), temperature coefficient of 5 ppm/° C, recommended preheating time of 15 minutes.

Typical applications include radar/LiDAR signal acquisition, partial discharge monitoring, non-destructive testing (NDT), fiber optic sensing demodulation, high-energy physics experiments, etc.

Hardware installation and environment preparation

2.1 Anti static and tool requirements

PXIe-9834 belongs to electrostatic sensitive equipment, and before installation, it is necessary to prepare:

Grounding anti-static pad and anti-static wristband.

Cross/Phillips screwdriver (preferably with magnetic head).

Ensure that the workbench is flat and well lit.

2.2 Chassis installation steps

Turn off the power of the PXIe chassis and unplug the power cord (hot plugging is strictly prohibited).

Push the module smoothly along the chassis rail until the backplane connector creates resistance.

Lift up the ejector handle to fully position the module and hear a "click" locking sound.

Secure the panel screws to ensure mechanical stability.

Connect all SMA cables (analog input, CLK IN, TRG IN) before powering on.

Packing list: Only module body and quick start guide. SMA cables need to be purchased separately, and it is recommended to use high-quality 50 Ω coaxial cables to maintain signal integrity.

2.3 Environmental conditions

Working temperature: 0 ° C to 50 ° C; Storage temperature: -20 ° C to 80 ° C.

Relative humidity: 5%~95% (no condensation).

Power consumption: standby about 5.46 W (+3.3V @ 18mA++12V @ 450mA), full load about 9.28 W (+3.3V @ 70mA++12V @ 753mA).

In depth analysis of analog front-end

3.1 Input Impedance and Coupling Selection

50 Ω mode: suitable for high-frequency signals (such as RF/microwave), matching the characteristic impedance of the transmission line to reduce reflection. Supports ranges of ± 0.5V, ± 1V, ± 5V (± 10V not available).

1M Ω mode: suitable for high impedance signal sources (such as oscilloscope probes, passive sensors), supporting all ranges (including ± 10V).

Coupling method:

DC coupling: complete transmission of DC components, suitable for measuring pulse baselines and slowly varying signals.

AC coupling: Blocking DC through high pass filtering to avoid high DC bias compression of dynamic range, suitable for measuring AC superimposed signals (note low-frequency cutoff characteristics).

3.2 Range and Data Format

The module adopts a 16 bit binary complement format, and the LSB value varies with the range:

± 10V range: LSB=0.305 mV (FSR-1LSB=9.99969 V)

±5V：0.153 mV

±1V：0.031 mV

±0.5V：0.015 mV

Positive full-scale corresponds to 0x7FFF, negative full-scale corresponds to 0x8000, and zero corresponds to 0x0000 (near the median:+1LSB=0x0001, -1LSB=0xFFFF). When programming, the driver API automatically completes the conversion between voltage and digital code.

3.3 Performance indicators (key parameters)

Signal to Noise Ratio (SNR): Typical values are 69 dB (± 0.5/± 1/± 5V range) and 65 dB (± 10V).

Total harmonic distortion (THD): -78 dB (full range).

Crosstalk: ≤ -80 dB (± 0.5V), ≤ -90 dB (± 1/± 5/± 10V), measurement conditions: 1 MHz sine wave, 90% full scale.

System noise: 0.1 mVrms at ± 0.5V range, 1.5 mVrms at ± 10V range.

Frequency response: The user manual provides typical amplitude frequency curves for impedances of 1M Ω and 50 Ω, showing a bandwidth of approximately 40 MHz at -3 dB and good passband flatness.

Trigger architecture and multi-mode detailed explanation

4.1 Overview of Trigger Sources

PXIe-9834 supports 7 types of trigger sources, which can be flexibly selected through software:

Description of minimum pulse width for triggering source signal type

Software triggers instant command - start immediately through API call

External digital trigger SMA TRG IN, TTL 3.3/5V tolerance for 20 ns rising/falling edge optional

Simulate triggering of any signal from CHO~CH3 with a 24 bit level setting for rising/falling edge condition triggering

PXI Trigger Bus [0:7] Backplane TTL 20 ns Module to Module Trigger Transmission

PXI STAR star trigger, TTL 20 ns precision low jitter trigger (issued by the system slot)

PXIe-DSTARB LVDS differential star trigger 20 ns extremely low latency (<150 ps slot to slot)

4.2 Simulation triggering details

The simulated trigger signal is obtained from the selected AI channel (CHO~CH3), independent of the acquisition channel. The trigger level is set at 16 bit resolution within the full range. Trigger condition:

Rising edge: The signal changes from below the trigger level to above the trigger level.

Falling edge: The signal changes from above the trigger level to below the trigger level.

This function does not require an external trigger line and is particularly suitable for event detection based on signal amplitude (such as partial discharge pulse triggering).

4.3 Trigger mode (timing control)

The module provides five triggering modes, covering almost all transient acquisition requirements:

Post Trigger: Collect N samples after triggering. The most common mode is used to record the response after an event occurs.

Delayed Trigger: After triggering, delay for a specified time (controlled by a 16 bit counter, with a step size of the time base period), and then collect N samples. Suitable for capturing signals with fixed delay after triggering.

Pre Trigger: Collect N samples before triggering. After initiating the pre trigger, the module continuously caches data until the triggering event arrives and stops. Used to observe a period of historical information before triggering (such as waveform before fault).

Middle Trigger: Simultaneously collect M samples before and N samples after triggering, and fully record the entire process before and after the event.

Re Trigger: In post trigger or delayed trigger mode, multiple triggering events are accepted, and a fixed number of samples are collected after each event, with all data stored continuously. The number of triggers can be set (R times, infinite if R=0). Minimum trigger interval: N+1 time base cycles in post trigger mode; In delayed triggering mode, it is (N+D)+1 time base cycle (D is the delay count). This mode is suitable for repetitive events (such as multi pulse train measurements).

Multi module synchronization (key feature)

In high channel systems such as array radar and multi-channel ultrasonic testing, multiple PXIe-9834 modules need to be synchronized. The module provides two synchronization mechanisms: trigger synchronization and time base synchronization.

5.1 Trigger synchronization

Implementing trigger signal distribution through PXI backplane:

Main module: Route internal triggers (software/external/analog) to a certain bit of PXI Trigger Bus [0.. 7] (set through software).

From module: Configure the trigger source to this bit (PXI Trigger Bus) and wait for the trigger to be received.

PXI STAR or PXIe-DSTARB can also be used, the latter having lower slot to slot skew (<150 ps), suitable for high-precision synchronization.

5.2 Time base synchronization

There are two schemes to ensure that the sampling clocks of multiple modules are of the same frequency and phase:

External reference clock: The main module or external signal source provides a 10 MHz reference clock, which is input through CLK IN and generates an 80 MHz ADC clock through onboard PLL. The same reference source can be received from the module (via backplane PXI_CLK10 or external allocation).

PXI Backplane 10 MHz: All modules can use PXI_CLK10 as a PLL reference to achieve full chassis clock synchronization without additional wiring.

Example of synchronous configuration:

Main module: using external digital triggering, while outputting the triggering signal to PXI_TRIG0; Time base selection internal PLL (locked to PXI_CLK10).

From module: Set the trigger source to PXI_TRIG0; The time base also selects PXI_CLK10 reference.

The sampling rate of all modules (set by the scan interval counter) must be consistent.

5.3 Synchronization precautions

When synchronizing external instruments, it is necessary to ensure that the cable lengths for triggering and clock signals match, and to add buffer drivers to reduce skew.

When synchronizing between modules, try to avoid reusing different signals on the PXI Trigger Bus to avoid conflicts.

The document provides a detailed synchronization architecture diagram (Figures 3-15 to 3-19), which engineers can refer to for configuration.

Clock and Sampling Rate Control

6.1 Internal Sampling Clock

By default, an onboard 80 MHz crystal oscillator (accuracy ± 25 ppm) is used, and frequency division sampling is achieved through a scanning interval counter (ScanIntrv), supporting any sampling rate from 1.22 kS/s to 80 MS/s (formula: sampling rate=80 MHz/ScanIntrv, ScanIntrv is 16 bits, range 1~65535). For example, setting ScanIntrv=2 yields 40 MS/s, and setting=65535 yields approximately 1.22 kS/s.

6.2 External Sampling Clock

When it is necessary to synchronize the sampling frequency with an external system (non 80 MHz integer division), an external sampling clock (frequency range of 10~80 MHz, AC coupling, 50 Ω input impedance, amplitude of 0.45~5 Vpp, duty cycle of 45%~55%) can be input through CLK IN SMA. When using an external sampling clock, it is necessary to call an API (such as WD_Config()) to reconfigure the ADC and ensure that the phase-locked loop is properly locked.

6.3 External reference clock

For applications that require strict synchronization of multiple modules, an external 10 MHz reference clock (via CLK IN) can be input, and an internal PLL can generate an 80 MHz clock. Alternatively, the PXI backplane 10 MHz (PXI_CLK10) can be directly used as a reference, which has extremely low deviation among all slots in the chassis.

DMA and Data Stream Management

The PXIe-9834 adopts PCIe Geni x4 interface, with a theoretical bandwidth of 1 GB/s (unidirectional), which is sufficient to support four channels of 80 MS/s x 16 bits=640 MB/s data flow.

7.1 Scatter‑Gather DMA

System memory is often difficult to allocate contiguous large blocks of memory. Modules support distributed aggregate DMA, which links multiple non contiguous physical memory blocks together through linked list descriptors to achieve high-capacity data transfer. Each descriptor contains a PCI address (supports 64 bits and can be mapped to over 4GB of memory), transfer length, and next descriptor pointer. The linked list can be reused to achieve multi buffer continuous acquisition (double buffer mode).

7.2 Counter Parameters

DataCnt: 31 bits, specifying the total number of samples collected (up to 2 ^ 31-1). When set to infinity, the module continuously collects data until the software stops.

TrigDelayTicks: 16 bits, used for delay triggering mode, measured in time base cycles.

Re trigger counter (ReTrgCnt): 31 bits, specifying the number of re triggers (0 means infinite).

Automatic calibration and maintenance

8.1 Calibration constant storage

PXIe-9834 is calibrated by the factory before leaving the factory, and the constant is written to Bank 0 (read-only) of the onboard EEPROM, with write protection to prevent misoperation. When the user performs self calibration, the new constant is written to Bank 1 (read-write). Default startup loading Bank 0; Users can specify the startup loading of Bank 1 through software (settings are saved in EEPROM and will not be lost upon power failure).

8.2 Self calibration process

Reason: Temperature changes and aging can cause offset and gain errors. It is recommended to perform this during the first installation of the module or when the ambient temperature changes significantly.

Requirement: Preheat for at least 20 minutes (internal temperature stable), disconnect all input cables (empty load).

Operation: Call the API to perform automatic calibration. The internal reference source of the module (1.8V/0.9V/0.45V, temperature coefficient 5 ppm/° C) is measured and path errors are corrected without the need for an external standard source.

Result: After calibration, Bank 1 is automatically updated, and the next startup can choose to load new constants.

Software ecosystem support

ADLINK provides the MAPS software suite, which includes three major components:

MAPS Core: Driver core and ACE management tool (configurable DMA buffer, device alias, and provides a soft panel for waveform preview).

MAPS/LV: LabVIEW library and examples, suitable for rapid graphical development.

MAPS/C: C/C++header files, API libraries, and examples (including trigger configuration, synchronization, data flow, etc.), suitable for high-performance customization.

All software can be downloaded from the ADLINK official website, and unauthorized versions can run in 2-hour demo mode. The commercial version requires purchasing authorization.

Typical application scenarios and configuration recommendations

Radar pulse capture: Using simulated triggering (rising edge, level threshold) to initiate acquisition, the medium triggering mode obtains a waveform segment before and after the pulse, combined with 1M Ω, ± 1V range, DC coupling, can accurately measure pulse width and amplitude.

Partial discharge monitoring: using high sensitivity ± 0.5V range, 50 Ω impedance (matched with high-frequency current transformer), external digital triggering (synchronous power frequency phase), and post triggering mode to continuously record multiple power frequency cycles.

Multi channel ultrasonic array: Synchronize 4 modules (a total of 16 channels), the main module outputs trigger to PXI_TRIG0, all modules use PXI_CLK10 as the reference clock, set the same ScanIntrv to ensure sampling synchronization error<1 ns.