ADLINK PXIe-9848 High Speed Digitizer Configuration Guide

ADLINK PXIe-9848 High Speed Digitizer: Architecture, Trigger, and Data Flow Optimization Guide

In high-speed transient measurement scenarios such as radar signal capture, LiDAR ranging, fiber optic testing, and partial discharge monitoring of power equipment, the sampling rate, bandwidth, dynamic range, and continuous flow disk capability of the data acquisition system directly determine the success or failure of the test. ADLINK PXIe-9848 is an 8-channel 14 bit 100 MS/s PXI Express high-speed digitizer with 100 MHz analog bandwidth, 512 MB onboard storage, and flexible input impedance (50 Ω/1M Ω software optional). It supports multiple trigger sources and trigger modes (including pre trigger, mid trigger, and re trigger), providing a powerful and flexible hardware platform for high-frequency signal acquisition. This article is aimed at test engineers and system integrators, detailing the engineering deployment and optimization methods of the module from dimensions such as module installation, front-end configuration (impedance/coupling/bandwidth limitations), trigger architecture, multi-mode acquisition timing, Scatter Gather DMA data stream, external clock synchronization, and automatic calibration, to help build a high-performance transient signal capture system.

Product positioning and core specifications

PXIe-9848 is an 8-channel single ended input high-speed digitizer that uses a 14 bit successive approximation ADC. Each channel supports up to 100 MS/s synchronous sampling without inter channel phase delay. Its key features include:

Analog input: 8-channel SMB interface, input impedance 50 Ω or 1M Ω (software switchable), coupling mode DC or AC (software selected), range ± 2V or ± 0.2V (software selected).

Bandwidth and filtering: -3 dB bandwidth can be selected from 100 MHz or 20 MHz (software adjustable) to adapt to different frequency signals and suppress high-frequency noise.

Onboard memory: 32 MB per channel (out of a total of 512 MB) FIFO, supporting burst acquisition and buffering of data streams.

Bus interface: PCI Express Gen1 x4, theoretical bandwidth of 1 GB/s, supports Scatter Gather DMA, and can achieve sustained high-speed data flow.

Trigger: software trigger, external digital trigger (SMA, adjustable trigger level 0.8 mV~3.3 V), analog trigger (any AI channel level detection) PXI Trigger Bus[0..7]、PXI_STAR、PXIe_DSTARB。

Trigger modes: post trigger, pre trigger, mid trigger, delayed trigger, all modes support re trigger.

Clock: Internal 100 MHz oscillator (with an accuracy of ± 25 ppm), can be used as a reference/sampling clock with PXI_CLK10 or PXle_CK100, supports multi module synchronization.

Calibration: Fully automatic calibration, built-in reference source, calibration constants stored in EEPROM (Bank0 factory read-only, Bank1 user writable).

Typical applications: radar intermediate frequency signal acquisition, fiber optic sensing demodulation, power supply module (PSU) dynamic testing, cable fault location, partial discharge monitoring.

Hardware installation and environment preparation

2.1 Anti static and tool requirements

PXIe-9848 is an electrostatic sensitive device, and before installation, it is necessary to:

Grounding anti-static pad and wristband.

Cross/Phillips screwdriver.

Check the appearance of the module for any physical damage.

2.2 Chassis installation steps

Turn off the power of the PXIe chassis and unplug the power cord (hot swapping is prohibited).

Push the module along the chassis rail until the backplane connector creates resistance.

Push up the ejector handle to fully position the module (hear a "click" sound).

Tighten the panel screws.

Connect all SMA cables (analog inputs CHO~CH7, external trigger TRG IN) before powering on.

Note: This module is compatible with PXI hybrid slots and can be installed in the peripheral slots of PXI or PXIe chassis.

2.3 Environmental conditions

Working temperature: 0 ° C~50 ° C; Storage temperature: -20 ° C~+80 ° C.

Relative humidity: 5%~95% (no condensation).

The power consumption is not explicitly listed, but PCIe x4 interface power supply usually meets the requirements.

Analog front end depth configuration

3.1 Input impedance selection

50 Ω mode: used for high-frequency signals (≥ MHz level), matching the characteristic impedance of the transmission line to reduce reflection. Suitable for scenarios where the signal source has an output impedance of 50 Ω (such as high-frequency function generators).

1M Ω mode: used for high impedance signal sources or short transmission lines to avoid load effects.

3.2 AC/DC coupling

DC coupling: preserves the DC component of the signal, suitable for measuring pulse baseline, DC bias, or low-frequency ramp signals.

AC coupling: blocks DC and only passes AC components, with a built-in high pass filter inflection point of about 10 Hz, suitable for measuring high-frequency superimposed signals, avoiding DC offset and compressing dynamic range.

3.3 Bandwidth limitation (20MHz/100MHz)

100 MHz bandwidth: captures high-frequency details, suitable for radar/communication signals.

20 MHz bandwidth limitation: Filter out high-frequency noise outside the band, improve signal-to-noise ratio (SNR), suitable for low-frequency signal measurement (such as power ripple, audio).