ADLINK DAQ/PXI-2000 series synchronous acquisition card configuration and triggering

Although single ended connection is simple, it has poor noise resistance and is only recommended for use when the number of channels is limited and signal quality requirements are not high.

Analog Input (A/D) Operation Theory and Trigger Mode

3.1 Sampling timing and scanning concept

Although DAQ/PXI-2000 is a synchronous sampling card (producing 4-channel samples in a single conversion), its internal logic follows a scan based design and still uses "scan" as the sampling unit. The sampling interval is controlled by SI_comounter (24 bits): Scan Interval=SI_comounter/TIMEBASE (default 40MHz internal clock or external 1-40MHz clock). For example, when SI_comounter=160, the sampling interval=160/40M=4 μ s (i.e. 250kS/s). For 2010, the minimum SI_comounter is 20 (2MS/s); In 2005, it was 80; In 2006, it was 160; In 2016, it was 50.

3.2 Detailed explanation of four triggering modes

The board provides software triggering, external digital triggering, external analog triggering, and SSI triggering, in conjunction with four acquisition modes:

Post trigger: The most commonly used mode is to collect a specified amount of scan data (PSC_comounter) after the triggering event occurs.

Pre trigger: Continuously collect data before triggering, and only retain the most recent M scan data after triggering (M is set by the M-counter). The 'enable' bit can control whether to wait for M scans before triggering, ensuring a sufficient amount of pre triggered data.

Middle trigger: Save a specified number of scans (before+after) before and after the trigger, suitable for scenes where the waveform before and after the event needs to be observed.

Delay trigger: After triggering an event, a specified time (controlled by Delay_counter, unit can be TIMEBASE or sampling clock cycle) is delayed before starting data collection. It is suitable for avoiding transient interference at the moment of triggering.

In addition, it supports Re trigger mode. In Post or Delay mode, PSC_comounter scans are collected after each trigger, waiting for the next trigger until the specified number of re triggers is reached.

3.3 Data Migration: Scatter/Gather DMA

The onboard A/D FIFO (8K for 2010, 512 samples for the rest), combined with the bus master DMA of the PLX IOP-480 PCI controller, can directly transfer data to the host memory with minimal CPU intervention. The Scatter/Gather feature allows linking discontinuous physical memory blocks into linked lists, supporting unlimited capacity collection and avoiding difficulties in allocating large contiguous memory blocks. The software driver automatically manages the descriptor chain, and users only need to set the sampling number and buffer.

3.4 Synchronous Digital Input (2010 only)

After the A/D conversion is completed, each channel of this model additionally latches 2 digital inputs (SDI<1:0>_X, a total of 8 lines), which are combined with 14 bit analog data to form a 16 bit word (the lower 2 bits are SDI). In terms of sampling timing, digital signals are latched within 220-400ns after conversion, which is basically synchronized with analog signals and suitable for applications that require simultaneous recording of digital states (such as trigger flags and encoders).

Analog output (D/A) and waveform generation

4.1 Software updates and timed waveform generation

Software update: Directly write to DAC register, suitable for static output or low-frequency control.

Timed waveform generation: Generate continuous or finite waveforms through internal counters (UI_comounter sets the update interval, UC_comounter sets the number of points per waveform, IC_comounter sets the number of iterations). The highest update rate is 1MS/s (UI_comounter ≥ 40, using a 40MHz internal clock).

4.2 Trigger and Iterative Output

Supports Post trigger, Delay trigger, and Re trigger, similar to A/D. The iterative function allows for repeated output of single waveform data (limited or unlimited). If the number of waveform points is less than the FIFO size (2K for 2010 and 512 for others), there is no need to repeatedly load data from the host, greatly saving PCI bandwidth. DLY2_comounter can set the interval between two iterations to generate complex waveforms such as pulse trains.

4.3 Stop Mode

When the software stops waveform generation, you can choose:

Mode I: Stop immediately;

Mode II: Stop after completing the current complete waveform (UC_comounter points);

Mode III: Stop after completing the current iteration cycle (IC_comounter complete waveforms).

These three modes enhance the controllability of waveform output and are suitable for different real-time requirements.

Universal Timer/Counter and Auxiliary Functions

The board provides two 16 bit independent timers/counters (GPTC0/1), supporting 8 working modes, including:

Simple Gate Control Event Counting (Mode 1)

Single cycle measurement (Mode 2)

Pulse Width Measurement (Mode 3)

Single pulse/trigger pulse/continuous pulse generation (Mode 4-8)

Each counter has an external clock input (up to 10MHz), gate control, and direction control, and the output can be used for external device synchronization or triggering other functions. These modes provide hardware level solutions for speed measurement, pulse counting, PWM generation, and more.