ADLINK PCIe-CPL64 Image Acquisition Card Hardware Trigger and Encoder Application

Trigger mode synchronized with encoder

PCIe-CPL64 supports multiple triggering methods to meet the different requirements of line array scanning and area array scanning. The triggering mode can be configured through the AKS aptureMode function or the CaptureMode field in the Camera File

Free Run: Continuous collection, not limited by external triggers, suitable for scenes with stable lighting and continuous motion.

Line Area Trigger: External TTL or RS422 trigger signals control the acquisition of each line or frame. The trigger source can be pin9/pin10 (TTL) or pin1-4 (RS422 differential) of CN3. SetLineAreaTriggerPolarity can be used to set the rising or falling edge trigger, and LineAreaTriggerStartEnable can be enabled to make the trigger signal only valid during the high-level enable period.

Encoder Input: Only applicable to linear scanning cameras, it controls line acquisition through pulses generated by an external encoder (A/B/Z three-phase) to achieve precise synchronization between image lines and physical motion positions. This is a key function for applications such as print inspection and roll surface inspection.

Encoder triggers detailed mechanism

The encoder input supports three modes (set through SetEncoder Input Mode):

A Phase: When an edge (rising or falling) of A phase is detected, a row of data acquisition is triggered.

AB Phase: Determine the direction of motion (CW or CCW) based on the phase difference between phase A and phase B. After each complete orthogonal period, trigger one line to achieve frequency doubling counting (1x/2x/4x).

ABZ Phase: The Z phase is used as the reference zero signal. When the Z phase is at a high level, the A/B phase starts counting and is used to establish an absolute position reference.

In addition, there are two key counters:

Encoder Delay Count: Ignoring the first N encoder pulses after starting the acquisition process, used to skip the acceleration phase during motion startup.

Encoder Compare Count: Each count of N valid pulses triggers a line acquisition, which is equivalent to pulse division. It is suitable for scenarios where high-resolution encoders need to reduce line density.

For example, if the encoder outputs 1000 pulses per millimeter and the camera needs to capture 200 lines per millimeter, set Encoder Compare Count to 5, which means capturing one line every 5 pulses to achieve a resolution of 5 μ m/line.

The counting direction of the encoder can be set to CW or CCW through SetEncoder Input Direction to accommodate differences in installation direction. There is also a hardware counter in the card (which can be read through the FHIR ncoderCounterValue), making it easy for software to monitor the current location.

Line triggered start signal

For applications that require external enable signals (such as starting data collection only after the material passes through the sensor), Line Trigger Start input (CN3 pin11/12) can be used. When this signal is at a high level, the trigger signal is allowed, otherwise it is blocked. Refer to Figure 2-4 in the manual for the timing diagram, which can effectively avoid image acquisition in invalid areas.

GPIO and External Control

PCIe-CPL64 provides 4 TTL digital inputs (DI0-3) and 4 open drain digital outputs (DO0-3). DI supports event triggering (enabled through SetDIEvent), and callback functions can be called when DI status changes to respond to external alarms or synchronization signals. DO is an open drain output, with no pull-up by default, but it can be enabled to internally pull up 10k Ω to+5V through SW2, making it convenient to directly drive low-power loads (maximum current of 100mA). If a large current needs to be driven, it is recommended to connect an external transistor or relay.

In addition, there are two Exposure Out signals that can directly output pulses synchronized with the internal exposure timing, used to control the external light source flicker and avoid heat generation and energy waste caused by continuous lighting.

Camera File Configuration and Parameter Explanation

PCIe-CPL64 uses a text-based Camera File (. cam) to store camera specific parameters, including sensor size, pixel count, tap count, trigger mode, CC1/CC2 control, etc. Users can load or modify it through the CamCreator tool, or manually edit it. The following key parameters are highlighted:

Sensor Tap: The number of camera output channels, such as single tap, dual tap, quad tap, etc. It is necessary to coordinate with SensorTapPlacement to specify the data arrangement order (such as odd sequence, start+middle, etc.).

PixelSize: The number of significant bits per pixel (8/10/12/14/16/24/30/36 bits). Note that if Tap=3 and PixelSize=8, it is in RGB24 color format.

PixelFormat: Unpack (raw data with padding bytes) or Pack (compressed without padding). Pack format reduces data volume but consumes CPU for reassembly.

CC1/CC2 Type: can be set as Pulse (pulse output) or DO (level output). In pulse mode, the pulse width and negative pulse width can be set to control the camera exposure or line period.

LVALEnable/DVALEnable: Camera Link standard signal line, used to indicate valid pixels or valid data, must be correctly enabled according to the camera manual.