Advanced triggering and multi card synchronization of ADLINK PCIe-CPL64V image acquisition card

Advanced triggering and multi card synchronization application of ADLINK PCIe-CPL64V image acquisition card

In the field of high-speed machine vision and industrial inspection, the Camera Link interface has long dominated high-end camera connectivity due to its high bandwidth, anti-interference, and standardization advantages. With the continuous improvement of image resolution and frame rate, traditional PCIe x4 acquisition cards are gradually facing challenges in throughput and synchronization accuracy. The PCIe-CPL64V series launched by ADLINK adopts PCIe Gen3 x4 architecture, supports Base/Medium/Full full configuration Camera Link, has a maximum aggregated data transfer rate of 850 MB/s, and integrates advanced functions such as multi card synchronization, programmable trigger chain, encoder position trigger, etc., providing a highly flexible hardware platform for linear scanning, 3D detection, and high-speed AOI systems. This article will provide engineers with a system level application reference from the dimensions of hardware architecture, trigger logic, CAM file configuration, multi card synchronization mechanism, and common debugging methods, to help them quickly solve difficult problems in practical deployment.

Product positioning and core upgrade highlights

PCIe-CPL64V is a fully upgraded version of the previous generation PCIe-CPL64, with major improvements including:

Doubling bus bandwidth: PCIe Gen3 x4 provides a theoretical bandwidth of approximately 3.9 GB/s, with an actual image transfer rate of 850 MB/s, making it easy to meet the full bandwidth requirements of 85MHz pixel clock in Full configuration (80 bits) (approximately 680 MB/s).

Memory expansion: Onboard 512 MB DDR cache, supporting longer burst collection and frame buffer queues, reducing the risk of frame loss.

I/O isolation enhancement: Provides 4-channel isolated digital input/output (500Vrms isolation), supports 10kHz input and 500kHz output, and adapts to strong interference environments in industrial sites.

Encoder interface upgrade: Differential isolated encoder input, supporting up to 20MHz (4x AB mode), compatible with multiple encoder protocols such as CW/CCW, OUT/DIR, etc.

Multi card synchronization: Supports up to 4 cards for synchronization, with a synchronization delay of less than 100ns, meeting the requirements of multi camera collaborative acquisition.

These features make it particularly suitable for high demand scenarios such as printing quality inspection, defect scanning for flat panel displays, and visual positioning for high-speed surface mount machines.

Trigger architecture: flexible and programmable signal chain

The triggering system of PCIe-CPL64V is its core competitiveness, and users can configure complex triggering chains through CAM files or APIs. The overall diagram can be found in Chapter 4 of the manual, and the core modules include:

1. Trigger Source Selection

Each output channel (4 DO and 2 CC control lines) can independently select trigger sources, including:

DI0~DI3 events: External isolated input, can be set with rising/falling edge triggering, and equipped with a debounce filter (0/200/500/800ns).

Encoder comparison event: triggered when the encoder count reaches the preset Compare Count.

Multi card synchronization event: The synchronization signal broadcasted by the main card, and the slave card listens for the event.

Software trigger: manually triggered through API.

This multi-source selection mechanism allows users to flexibly combine external sensors, encoder positions, and software instructions to adapt to complex automation processes.

2. Trigger Delay

Each output channel can be independently configured with a delay mode:

Timer mode: Set a fixed delay time in units of 1 μ s (maximum approximately 16.7 seconds).

Encoder mode: Delay the specified number of encoder pulses (up to 32 bits) to achieve position dependent delay, such as waiting for a fixed physical distance to trigger camera exposure after detecting material edges.

3. Re trigger

This function automatically generates a predefined number of output pulses after a single external trigger, especially suitable for linear scanning cameras. For example, when an external sensor triggers once, 1024 CC1 pulses (one per line) need to be continuously sent to the camera to complete the acquisition of one frame of image. By setting Retrigger. Enable=True and specifying the number and interval of triggers (encoder count or timer), the hardware automatically completes the entire sequence without CPU intervention, greatly improving real-time performance.

4. Output PWM generation

Each DO and CC channel can be configured for manual mode or trigger mode. In trigger mode, the high-level and low-level widths of the output pulse can be independently set (1 μ s resolution) for precise control of light source flicker or camera exposure timing.

This modular design allows engineers to achieve full chain timing matching from external events to camera control without writing complex logic, solely through CAM files.

CAM file configuration: from templates to customization

The CAM file (in. ini format) is the core configuration file of PCIe-CPL64V, which defines all operational parameters such as image format, trigger behavior, encoder parameters, I/O mapping, etc. Users can load templates and modify them through the CamCreator tool, or directly edit text files. The following focuses on analyzing several chapters that are prone to errors or require special attention.