Advanced triggering and multi card synchronization of ADLINK PCIe-CPL64V image acquisition card

1. [ImageFormat] Image format and bandwidth limitations

SensorWidth/SensorHeight: Specific alignment multiple requirements must be met, for example, when Mono8 x 1/2/4/8tap, the width must be a multiple of 32; When Mono10 x 8tap, the width needs to be a multiple of 320. If it does not meet the requirements, an error will be reported when the collection starts.

CameraConfiguration: Select Base, Medium, or Full based on the actual connected camera configuration, corresponding to different data bit widths and required cable numbers (see manual table). Incorrect configuration can cause abnormal status of LED7 (orange flashing indicates error).

TapPlacement: It is necessary to match the actual output mode of the camera (single/double/four/eight/ten tap), otherwise the image arrangement will be disordered.

Practical tip: Use LED7 status indicator light to quickly diagnose configuration: Green constant light=Full, green flashing (2Hz)=Medium, orange constant light=Base, orange flashing=Abnormal, off=No camera detected.

2. [TriggerInput] triggers input debounce

When using mechanical switches or relay contacts as trigger sources, shaking may cause false triggering. Setting DebounceTime (200/500/800ns) can effectively filter out glitches, but it should be noted that a long debounce time may delay the response and needs to be balanced based on the actual signal frequency.

3. [Encoder Input] Encoder mode and comparison value

Mode: Supports multiple modes such as AB phase X1/X2/X4, CW/CCW, OUT/DIR, etc., and needs to match the output type of the encoder.

Comparing Count: When the encoder count reaches this value, a comparison event is generated, which can be used as one of the trigger sources. Real time position can be monitored by reading the status parameters of Encoder Counter.

4. [Retrigger] Re trigger setting instance

Assuming a linear camera is used, the rising edge of the external DI0 triggers one frame acquisition, requiring 2048 lines per frame, and the encoder triggers one line every 10 pulses. Then configure:

text

[TriggerOutputTrigSrc]

DO0TriggerSource=DI0 # DI0 as initial trigger

[Retrigger]

Port0CC1RetriggerEnable = True

Port0CC1Mode = EncoderMode

Port0CC1TriggerNums = 2048

Port0CC1Interval=10 # CC1 is triggered every 10 encoder pulses

In this way, when DI0 is triggered once, the hardware automatically outputs 2048 CC1 pulses to the camera continuously at intervals of encoder pulses, completing the entire frame acquisition.

Multi card synchronization: precise timing and low latency

When multiple cameras are needed for simultaneous shooting (such as binocular stereo vision or multi angle detection), PCIe-CPL64V provides inter board synchronization mechanism, supporting up to 4 cards for synchronization with synchronization jitter less than 100ns.

Hardware connection: All cards are cascaded through a CN4 dedicated ribbon cable, distinguishing between master and slave cards. The main card's CN4 outputs a synchronization signal, and the secondary card's CN4 receives the signal.

CAM file configuration:

Master card setting [MultiCardSync] Mode=Master

From Card Settings [MultiCardSync] Mode=Slave

In [MultiCardTrigSrc], the master card selects the trigger source (such as DI0), and the slave card selects TriggerSource=MultiCardSync.

Power on timing: The master card needs to start collecting data before the slave card to ensure stable synchronization signals. The current mode (1=Master, 0=Slave) can be verified through the state parameter MultiCardSync Mode.

Troubleshooting: If synchronization fails, check if the CN4 cable is locked, if the card ID conflicts (SW1 must be unique), and if the main card is generating synchronization events normally (observe LED2: the main card is always red and the slave card is always green). If LED2 on the card does not light up, it means that no synchronization signal has been received and the hardware connection or CAM file configuration needs to be checked.

PoCL power supply and safety testing

PCIe-CPL64V supports Power over Camera Link, and each SDR interface can output+12V/0.8A. The automatic detection function can identify non PoCL cables or cameras to avoid damage. However, some PoCL devices may not comply with standard timing, causing voltage startup or drop beyond the tolerance range. In this case, the PoCL SafePower Status parameter will report an error (non-zero value), and the corresponding Clock Startup Time Tolerance, Clock Drop Out Time Tolerance, and Voltage Drop Duration Tolerance can be manually adjusted (in μ s) to relax the detection conditions. These tolerances can be pre-set in the CAM file to be compatible with non-standard devices.

Attention: If the PoCL power indicator light (LED next to LED7) does not light up, first check if the cable is PoCL compatible (all 26 cores are intact), and then try to force the PowerState setting (but be cautious).

State parameters and debugging tools

Chapter 6 of the manual lists a wealth of status registers, which can be read through AVSAdvancedConfigRead and are extremely useful for on-site debugging:

DataStreamStatus: Indicates whether the FPGA is receiving data from the front-end and transmitting data to the host, quickly locating data flow blocking points.