ADLINK PXIe-9848 High Speed Digitizer Configuration Guide



ADLINK PXIe-9848 High Speed Digitizer: Architecture, Trigger, and Data Flow Optimization Guide

In high-speed transient measurement scenarios such as radar signal capture, LiDAR ranging, fiber optic testing, and partial discharge monitoring of power equipment, the sampling rate, bandwidth, dynamic range, and continuous flow disk capability of the data acquisition system directly determine the success or failure of the test. ADLINK PXIe-9848 is an 8-channel 14 bit 100 MS/s PXI Express high-speed digitizer with 100 MHz analog bandwidth, 512 MB onboard storage, and flexible input impedance (50 Ω/1M Ω software optional). It supports multiple trigger sources and trigger modes (including pre trigger, mid trigger, and re trigger), providing a powerful and flexible hardware platform for high-frequency signal acquisition. This article is aimed at test engineers and system integrators, detailing the engineering deployment and optimization methods of the module from dimensions such as module installation, front-end configuration (impedance/coupling/bandwidth limitations), trigger architecture, multi-mode acquisition timing, Scatter Gather DMA data stream, external clock synchronization, and automatic calibration, to help build a high-performance transient signal capture system.

Product positioning and core specifications

PXIe-9848 is an 8-channel single ended input high-speed digitizer that uses a 14 bit successive approximation ADC. Each channel supports up to 100 MS/s synchronous sampling without inter channel phase delay. Its key features include:

Analog input: 8-channel SMB interface, input impedance 50 Ω or 1M Ω (software switchable), coupling mode DC or AC (software selected), range ± 2V or ± 0.2V (software selected).

Bandwidth and filtering: -3 dB bandwidth can be selected from 100 MHz or 20 MHz (software adjustable) to adapt to different frequency signals and suppress high-frequency noise.

Onboard memory: 32 MB per channel (out of a total of 512 MB) FIFO, supporting burst acquisition and buffering of data streams.

Bus interface: PCI Express Gen1 x4, theoretical bandwidth of 1 GB/s, supports Scatter Gather DMA, and can achieve sustained high-speed data flow.

Trigger: software trigger, external digital trigger (SMA, adjustable trigger level 0.8 mV~3.3 V), analog trigger (any AI channel level detection) PXI Trigger Bus[0..7]、PXI_STAR、PXIe_DSTARB。

Trigger modes: post trigger, pre trigger, mid trigger, delayed trigger, all modes support re trigger.

Clock: Internal 100 MHz oscillator (with an accuracy of ± 25 ppm), can be used as a reference/sampling clock with PXI_CLK10 or PXle_CK100, supports multi module synchronization.

Calibration: Fully automatic calibration, built-in reference source, calibration constants stored in EEPROM (Bank0 factory read-only, Bank1 user writable).

Typical applications: radar intermediate frequency signal acquisition, fiber optic sensing demodulation, power supply module (PSU) dynamic testing, cable fault location, partial discharge monitoring.

Hardware installation and environment preparation

2.1 Anti static and tool requirements

PXIe-9848 is an electrostatic sensitive device, and before installation, it is necessary to:

Grounding anti-static pad and wristband.

Cross/Phillips screwdriver.

Check the appearance of the module for any physical damage.

2.2 Chassis installation steps

Turn off the power of the PXIe chassis and unplug the power cord (hot swapping is prohibited).

Push the module along the chassis rail until the backplane connector creates resistance.

Push up the ejector handle to fully position the module (hear a "click" sound).

Tighten the panel screws.

Connect all SMA cables (analog inputs CHO~CH7, external trigger TRG IN) before powering on.

Note: This module is compatible with PXI hybrid slots and can be installed in the peripheral slots of PXI or PXIe chassis.

2.3 Environmental conditions

Working temperature: 0 ° C~50 ° C; Storage temperature: -20 ° C~+80 ° C.

Relative humidity: 5%~95% (no condensation).

The power consumption is not explicitly listed, but PCIe x4 interface power supply usually meets the requirements.

Analog front end depth configuration

3.1 Input impedance selection

50 Ω mode: used for high-frequency signals (≥ MHz level), matching the characteristic impedance of the transmission line to reduce reflection. Suitable for scenarios where the signal source has an output impedance of 50 Ω (such as high-frequency function generators).

1M Ω mode: used for high impedance signal sources or short transmission lines to avoid load effects.

3.2 AC/DC coupling

DC coupling: preserves the DC component of the signal, suitable for measuring pulse baseline, DC bias, or low-frequency ramp signals.

AC coupling: blocks DC and only passes AC components, with a built-in high pass filter inflection point of about 10 Hz, suitable for measuring high-frequency superimposed signals, avoiding DC offset and compressing dynamic range.

3.3 Bandwidth limitation (20MHz/100MHz)

100 MHz bandwidth: captures high-frequency details, suitable for radar/communication signals.

20 MHz bandwidth limitation: Filter out high-frequency noise outside the band, improve signal-to-noise ratio (SNR), suitable for low-frequency signal measurement (such as power ripple, audio).

3.4 Range and Data Format

The module provides two ranges of ± 2V and ± 0.2V (selected through software), and 14 bit ADC data is transmitted in 16 bit binary complement format (the lower 2 bits need to be truncated, and the actual effective bits are 14 bits).

± 2V range: LSB=244.14 μ V, positive full-scale 0x7FFF corresponds to+1.999756 V, negative full-scale 0x8000 corresponds to -2 V.

± 0.2V range: LSB=24.41 μ V, corresponding to ± 0.199975 V.

When programming, the driver API automatically completes the conversion between voltage and digital code.

Trigger architecture and multi-mode acquisition

4.1 Overview of Trigger Sources

PXIe-9848 supports the following trigger sources (all channels share the same trigger source):

Key parameters of trigger source signal type

Software triggers instant commands -

External digital trigger SMA TRG IN, TTL compatible trigger level adjustable (0.8 mV~3.3 V, 12 bit step), default 1.67 V; polarity up/down optional; Minimum pulse width of 20 ns

Simulate triggering any AI channel (CHO~CH7) with a 14 bit adjustable trigger level and rising/falling edge conditions

PXI Trigger Bus [0:7] Backplane TTL Multi Module Synchronous Trigger Transmission

PX_STAR star triggered (TTL) low jitter, minimum pulse width of 20 ns

PXIe-DSTARB LVDS differential star trigger with extremely low slot to slot skew, suitable for high-precision synchronization

External digital trigger highlights: The trigger level can be programmed through software, with a range of 0.8 mV~3.3 V and a step size of 0.8 mV, greatly enhancing trigger flexibility. For example, it can be set to a threshold of 1.2 V to match specific logic levels.

4.2 Simulation triggering details

The simulated trigger signal is obtained from the selected channel without affecting the normal acquisition of that channel. The trigger level can be set at a 14 bit resolution within the full range (refer to the table), supporting rising edge (signal rising crossing trigger level) or falling edge (falling crossing trigger level) triggering.

4.3 Trigger mode (timing control)

The module provides five triggering modes, covering various transient capture requirements:

Post Trigger: Collecting N samples after triggering is the most commonly used mode.

Pre Trigger: Collect M samples before triggering to observe the signal condition before triggering (such as the waveform before the fault). After startup, the module continues to cache until a triggering event occurs.

Middle Trigger: Simultaneously collect M samples before and N samples after triggering, and fully record the process before and after the event. Note: The triggering event must occur after the pre collected data volume (M samples) is full, otherwise the triggering will be ignored.

Delayed Trigger: After triggering, a specified time (set by a 16 bit delay counter, measured in time base cycles, with a maximum delay of approximately (2 ^ 16) cycles) is delayed before collecting N samples.

Re Trigger: In post trigger or delayed trigger mode, the number of repeated triggers can be set (R times, infinite if R=0), with a fixed number of samples collected each time and all data stored continuously. The minimum interval between two triggers depends on the sampling rate and counter settings (specific formulas are not provided in the document, but it is usually necessary to ensure that the previous acquisition is completed).

4.4 Trigger Output (Multi Module Synchronization)

PXIe-9848 can serve as the main module, routing internal trigger signals (software/external/analog) to any bit of the PXI Trigger Bus to synchronize with other slave modules inside the chassis.

Clock and Time Base Control

5.1 Time Base Source Options

Internal 100 MHz oscillator: default, accuracy ± 25 ppm.

PXI_CLK10: Backplane 10 MHz reference clock, multiplied to 100 MHz through PLL, with delay matching between all slots<1 ns, suitable for single box multi module synchronization.

PXle_CK100: Backplane 100 MHz differential clock, delay matching<200 ps, suitable for higher precision synchronization.

5.2 Sampling rate adjustment

The sampling rate is fixed at 100 MS/s (based on internal time base), and downsampling is achieved through a scanning interval counter (ScanIntrv): sampling rate=100 MHz/ScanIntrv (ScanIntrv is 16 bits, with a value range of 1~65535). Therefore, the sampling rate can be continuously adjusted between approximately 1.025 kS/s (100M/65535) and 100 MS/s. For example, ScanIntrv=2 yields 50 MS/s, while ScanIntrv=3 yields 33.33 MS/s.

5.3 External Clock (This model does not directly support external sampling clock input)

The document does not mention CLK IN as an external sampling clock input, and only supports internal oscillators or backplane reference clocks (PXI_CLK10/PXle_CK100) as time base sources. The final ADC clock is fixed at 100 MHz (multiplied by PLL). Therefore, if frequency synchronization with external systems is required, it can only be achieved through reference clock synchronization (10 MHz or 100 MHz), and non 100 MHz sampling clocks cannot be directly input.

DMA and Data Stream Management

6.1 Data bandwidth challenge

100 MS/s x 14 bits per channel ≈ 1.4 Gbps, with a total data rate of approximately 11.2 Gbps (1.4 GB/s) for 8 channels. PCIe Geni x4 has a theoretical bandwidth of 1 GB/s (unidirectional), so it cannot achieve infinite continuous streaming at full speed on all channels. Solution:

Reduce the number of working channels (for example, using only 4 channels, reducing the data rate to about 0.7 GB/s, which can meet continuous flow).

Reduce the sampling rate (by adjusting ScanIntrv).

Utilizing an onboard 512 MB FIFO as a buffer to achieve burst acquisition.

6.2 Scatter‑Gather DMA

The module supports decentralized aggregation DMA, which links non contiguous physical memory blocks together through linked list descriptors to achieve efficient transfer of large blocks of data. Each descriptor contains a 64 bit PCI address, transmission length, and next descriptor pointer. The linked list can be reused and supports continuous collection with multiple buffers. In non SG mode, the maximum single transfer is 8 MB; in SG mode, there is no size limit (only limited by system memory capacity).

6.3 Data Counter and Trigger Count

DataCnt: 32-bit, specifying the number of samples collected per channel (up to approximately 536 million).

TrigDelayTicks: 16 bits, used for delay trigger mode.

Re trigger counter (ReTrgCnt): 32-bit, set the number of re triggers (0 means infinite).

Automatic calibration and maintenance

7.1 Calibration constant storage

PXIe-9848 undergoes factory calibration before leaving the factory, with a constant written to EEPROM's Bank 0 (read-only) and write protection to prevent misoperation. When the user performs self calibration, the new constant is written to Bank 1 (read-write). By default, Bank 1 is loaded (contrary to some other models, please refer to the documentation). Users can specify to start loading Bank 0 or Bank 1 through software, and this setting is saved in EEPROM.

7.2 Self calibration process

Necessity: Temperature changes and aging can cause offset/gain drift. It is recommended to perform the module installation for the first time or when there are significant changes in ambient temperature.

Preparation: Preheat for at least 20 minutes and disconnect all input cables (empty load).

Operation: Call the API to perform automatic calibration, and the internal reference source (stable low drift) of the module is used to correct errors without external reference.

Result: The calibration constant has been updated to Bank 1 and can be used on the next startup.

Software support ecosystem

PXIe-9848 supports ADLINK traditional software development suite:

WD-DASK: Drivers and DLLs for Windows 2000/XP/Vista/7, compatible with programming environments such as VB/VC+/BCB/Delphi.

DAQPilot: Supports multiple languages under Windows (VB.net, VC.net, etc.) and provides LabVIEW and MATLAB adapters.

All software is included in the ADLINK All in One CD, and unauthorized versions can be tested for 2 hours.

Typical Application Configuration Example

Radar intermediate frequency signal capture: using 50 Ω impedance, 100MHz bandwidth, ± 2V range, DC coupling, analog triggering (rising edge, threshold 0.5V), medium triggering mode (pre acquisition of 1024 points, post acquisition of 4096 points), ScanIntrv=1（100MS/s）， Enable 4 channels, with a data rate of approximately 0.7GB/s, capable of continuous streaming.

Dynamic testing of power module: using 1M Ω impedance, 20MHz bandwidth limitation, ± 0.2V range (high sensitivity), AC coupling (removing DC bias), external digital triggering (rising edge, triggering level 1.5V), delayed triggering mode (delayed by 10 μ s), single channel acquisition, ScanIntrv=10（10MS/s）， Continuously store to SSD.

Multi module synchronization (extended from 8 channels to 16 channels): The main module sets the trigger source as an external digital trigger, and the trigger output is sent to PXI_TRIG0; All module time bases are selected as PXI_CLK10; Set the trigger source from the module to PXI_TRIG0; Unified ScanIntrv settings to ensure consistent sampling rates.