ADLINK PXIe-9852 High Speed Digitizer Configuration Guide

ADLINK PXIe-9852 High Speed Digitizer: Architecture, Trigger, and Data Average Mode Application Guide

In high-speed transient measurement fields such as distributed temperature sensing (DTS), laser radar (LiDAR) ranging, radar intermediate frequency acquisition, and power cable fault location, sampling rate and dynamic range are often contradictory. ADLINK PXIe-9852 is a 2-channel 14 bit 200 MS/s PXI Express high-speed digitizer that combines 90 MHz analog bandwidth, flexible input impedance (50 Ω/1M Ω), multi range (± 0.2V/± 2V/± 10V), and 1 GB onboard storage. It also provides a unique Data Average Mode, which can improve effective resolution through oversampling under re triggering conditions. This article is aimed at testing system engineers, providing a complete engineering deployment and optimization guide from the dimensions of hardware installation, front-end configuration, trigger source and mode (including pre trigger, medium trigger, and re trigger), data averaging mode principle, multi module synchronization (including pre-data-ready handshake), clock architecture (internal/external reference/sampling clock), and automatic calibration.

Product positioning and core specifications

PXIe-9852 is a 2-channel digitizer designed specifically for high sampling rate and high-precision transient signal capture. It uses a 14 bit successive approximation ADC and can synchronously sample up to 200 MS/s per channel. Its core features include:

Analog input: 2-channel SMA single ended input, input impedance 50 Ω or 1M Ω (software switchable), coupling mode DC or AC (software selected, AC inflection point 11 Hz), range ± 0.2V, ± 2V or ± 10V (software selected).

Bandwidth: -3 dB. Typical bandwidth is 90 MHz (both 50 Ω and 1 M Ω can be achieved).

Onboard memory: 1 GB FIFO, supports long-term burst acquisition.

Bus interface: PCI Express Gen2 x4, theoretical bandwidth of 2 GB/s (unidirectional), combined with Scatter Gather DMA, can easily handle two channel full speed data streams (200 MS/s x 14 bits x 2 ≈ 5.6 Gbps ≈ 700 MB/s, much lower than Gen2 x4 bandwidth).

Clock: Internal 10 MHz oscillator (synthesized by PLL to 200 MHz), external reference clock (10 MHz) or external sampling clock (40 MHz~200 MHz) input through CLK IN, supporting both PXI-CLK10 and PXle_CK100 backplane clocks.

Trigger: software trigger, external digital trigger (SMA TRG IN, TTL compatible, pulse width ≥ 20 ns), analog trigger (CHO/CH1 level detection) PXI Trigger Bus[0..7]、PXI_STAR、PXIe_DSTARB， And it has trigger output (TRG OUT, pulse width programmable 50 ns~10 μ s).

Trigger modes: post trigger, delayed trigger, pre trigger, medium trigger, all modes support re trigger.

Data averaging mode: In only post trigger/delayed trigger mode, the waveform collected from multiple repeated triggers is averaged point by point, and 16 bit or 32-bit data is output to improve effective resolution (consistent signal repeatability is required).

Calibration: Fully automatic calibration, built-in reference source (+5V/+2.5V, temperature coefficient 3.0 ppm/° C), recommended preheating for 15 minutes, calibration constant stored in EEPROM (Bank0 read-only factory, Bank1 user writable).

Typical applications: Distributed Temperature Sensing (DTS), video IC testing, physics laboratory research, cable fault location, and partial discharge monitoring.

Hardware installation and environment preparation

2.1 Anti static and Tools

PXIe-9852 is an electrostatic sensitive device, and grounding anti-static pads, wristbands, and Phillips/Phillips screwdrivers need to be prepared before installation. Check the appearance of the module for any physical damage.

2.2 Chassis installation steps

Turn off the power of the PXIe chassis and unplug the power cord (hot plugging is strictly prohibited).

Push the module along the chassis rail until the backplane connector creates resistance.

Push up the ejector handle to fully position the module (hear a "click" sound).

Tighten the panel screws.

Connect all SMA cables (CHO/CH1 analog input, CLK IN, TRG IN, TRG OUT) before powering on.

Attention: The module is compatible with PXI hybrid slots and can be installed in the peripheral slots of PXI or PXIe chassis.

2.3 Environment and Power Consumption

Working temperature: 0 ° C~55 ° C; Storage temperature: -20 ° C~+80 ° C; Humidity: 5%~95% (no condensation).

Power consumption:+3.3V @ 76mA and+12V @ 88mA in standby mode; At full load,+3.3V @ 678mA and+12V @ 970mA, with a total power consumption of approximately 14W.

Detailed description of analog front-end configuration

3.1 Input impedance selection

50 Ω: Match high-frequency transmission lines (such as 50 Ω coaxial cables) to reduce signal reflection, suitable for high-frequency signal sources (≥ MHz).

1M Ω: Used for high impedance signal sources or short distance transmission to avoid loading effects.

3.2 AC/DC coupling

DC coupling: retaining the DC component, suitable for measuring pulse baselines and slowly changing signals.

AC coupling: blocks DC and only passes through AC components, with a high pass inflection point of 11 Hz, suitable for measuring high-frequency signals with superimposed DC bias.