ADLINK PXIe-9852 High Speed Digitizer Configuration Guide

ADLINK PXIe-9852 High Speed Digitizer: Architecture, Trigger, and Data Average Mode Application Guide

In high-speed transient measurement fields such as distributed temperature sensing (DTS), laser radar (LiDAR) ranging, radar intermediate frequency acquisition, and power cable fault location, sampling rate and dynamic range are often contradictory. ADLINK PXIe-9852 is a 2-channel 14 bit 200 MS/s PXI Express high-speed digitizer that combines 90 MHz analog bandwidth, flexible input impedance (50 Ω/1M Ω), multi range (± 0.2V/± 2V/± 10V), and 1 GB onboard storage. It also provides a unique Data Average Mode, which can improve effective resolution through oversampling under re triggering conditions. This article is aimed at testing system engineers, providing a complete engineering deployment and optimization guide from the dimensions of hardware installation, front-end configuration, trigger source and mode (including pre trigger, medium trigger, and re trigger), data averaging mode principle, multi module synchronization (including pre-data-ready handshake), clock architecture (internal/external reference/sampling clock), and automatic calibration.

Product positioning and core specifications

PXIe-9852 is a 2-channel digitizer designed specifically for high sampling rate and high-precision transient signal capture. It uses a 14 bit successive approximation ADC and can synchronously sample up to 200 MS/s per channel. Its core features include:

Analog input: 2-channel SMA single ended input, input impedance 50 Ω or 1M Ω (software switchable), coupling mode DC or AC (software selected, AC inflection point 11 Hz), range ± 0.2V, ± 2V or ± 10V (software selected).

Bandwidth: -3 dB. Typical bandwidth is 90 MHz (both 50 Ω and 1 M Ω can be achieved).

Onboard memory: 1 GB FIFO, supports long-term burst acquisition.

Bus interface: PCI Express Gen2 x4, theoretical bandwidth of 2 GB/s (unidirectional), combined with Scatter Gather DMA, can easily handle two channel full speed data streams (200 MS/s x 14 bits x 2 ≈ 5.6 Gbps ≈ 700 MB/s, much lower than Gen2 x4 bandwidth).

Clock: Internal 10 MHz oscillator (synthesized by PLL to 200 MHz), external reference clock (10 MHz) or external sampling clock (40 MHz~200 MHz) input through CLK IN, supporting both PXI-CLK10 and PXle_CK100 backplane clocks.

Trigger: software trigger, external digital trigger (SMA TRG IN, TTL compatible, pulse width ≥ 20 ns), analog trigger (CHO/CH1 level detection) PXI Trigger Bus[0..7]、PXI_STAR、PXIe_DSTARB， And it has trigger output (TRG OUT, pulse width programmable 50 ns~10 μ s).

Trigger modes: post trigger, delayed trigger, pre trigger, medium trigger, all modes support re trigger.

Data averaging mode: In only post trigger/delayed trigger mode, the waveform collected from multiple repeated triggers is averaged point by point, and 16 bit or 32-bit data is output to improve effective resolution (consistent signal repeatability is required).

Calibration: Fully automatic calibration, built-in reference source (+5V/+2.5V, temperature coefficient 3.0 ppm/° C), recommended preheating for 15 minutes, calibration constant stored in EEPROM (Bank0 read-only factory, Bank1 user writable).

Typical applications: Distributed Temperature Sensing (DTS), video IC testing, physics laboratory research, cable fault location, and partial discharge monitoring.

Hardware installation and environment preparation

2.1 Anti static and Tools

PXIe-9852 is an electrostatic sensitive device, and grounding anti-static pads, wristbands, and Phillips/Phillips screwdrivers need to be prepared before installation. Check the appearance of the module for any physical damage.

2.2 Chassis installation steps

Turn off the power of the PXIe chassis and unplug the power cord (hot plugging is strictly prohibited).

Push the module along the chassis rail until the backplane connector creates resistance.

Push up the ejector handle to fully position the module (hear a "click" sound).

Tighten the panel screws.

Connect all SMA cables (CHO/CH1 analog input, CLK IN, TRG IN, TRG OUT) before powering on.

Attention: The module is compatible with PXI hybrid slots and can be installed in the peripheral slots of PXI or PXIe chassis.

2.3 Environment and Power Consumption

Working temperature: 0 ° C~55 ° C; Storage temperature: -20 ° C~+80 ° C; Humidity: 5%~95% (no condensation).

Power consumption:+3.3V @ 76mA and+12V @ 88mA in standby mode; At full load,+3.3V @ 678mA and+12V @ 970mA, with a total power consumption of approximately 14W.

Detailed description of analog front-end configuration

3.1 Input impedance selection

50 Ω: Match high-frequency transmission lines (such as 50 Ω coaxial cables) to reduce signal reflection, suitable for high-frequency signal sources (≥ MHz).

1M Ω: Used for high impedance signal sources or short distance transmission to avoid loading effects.

3.2 AC/DC coupling

DC coupling: retaining the DC component, suitable for measuring pulse baselines and slowly changing signals.

AC coupling: blocks DC and only passes through AC components, with a high pass inflection point of 11 Hz, suitable for measuring high-frequency signals with superimposed DC bias.

3.3 Range and Data Format

The module supports three ranges of ± 0.2V, ± 2V, and ± 10V (software selection). 14 bit ADC data is transmitted in 16 bit binary complement format (the lower 2 bits are fixed to 0 and need to be truncated).

± 10V range: LSB=1.22 mV, positive full-scale 0x7FFC corresponds to+9.99878 V, negative full-scale 0x8000 corresponds to -10 V.

± 2V range: LSB=0.244 mV.

± 0.2V range: LSB=24.4 μ V.

The driver API automatically completes the conversion between voltage and digital code.

3.4 Performance indicators

Bandwidth: 90 MHz (typical value), the amplitude frequency curve is shown in Figure 1-1 (± 0.2Vpp) and Figure 1-2 (± 2Vpp) of the manual.

SNR: 56 dB at ± 0.2V and 62 dB at ± 2V/± 10V under 1M Ω; 60 dB at ± 0.2V and 62 dB at ± 2V under 50 Ω.

Overvoltage protection: ± 10V (1M Ω) or ± 10V sine wave/7Vrms peak<10V (50 Ω).

Trigger architecture and multi-mode acquisition

4.1 Overview of Trigger Sources

All trigger sources can be selected by software, and the trigger polarity (rising/falling) can be set:

Software trigger: API call takes effect immediately.

External digital trigger: SMA TRG IN, 3.3V TTL (5V tolerance), threshold VIH=2.0V, VIL=0.8V, minimum pulse width of 20 ns.

PX_STAR: Backplane star trigger, TTL compatible, low jitter.

PXIe-DSTARB: LVDS differential star trigger, extremely low slot to slot skew.

PXI Trigger Bus [0.. 7]: Backplane 8-bit parallel bus, which can be used for multi module trigger distribution.

Simulated trigger: Select the channel monitoring level from CH0 or CH1, and the trigger level is software adjustable (14 bit resolution).

Trigger output (TRG OUT): Whenever the acquisition starts, output a pulse synchronized with Timebase, with a programmable pulse width of 50 ns, 100 ns, 150 ns, 200 ns, 500 ns, 1 μ s, 2 μ s, 7.5 μ s, or 10 μ s, which can drive a 50 Ω load (5V TTL).

4.2 Trigger Mode

Post Trigger: Collect N samples after triggering (most commonly).

Delayed Trigger: After triggering, the data is collected after a specified delay time (set by a 16 bit delay counter with a step size of the time base period).

Pre Trigger: Collect M samples before triggering to capture the history before triggering.

Middle Trigger: Simultaneously collect M samples before triggering and N samples after triggering.

Re Trigger: In post trigger or delayed trigger mode, the number of repeated triggers R can be set (R=0 means infinite), and N samples are collected and stored continuously for each trigger. Minimum triggering interval: The post triggering mode is N+8 time base cycles; The delay triggering mode is (N+D)+8 time base cycles (D is the delay count).

4.3 Data averaging mode (core feature)

Principle: In post trigger or delayed trigger mode, if the number of re triggers R is set, the module will collect waveforms with a length of N in the R segment (N samples per trace). The data averaging mode averages R traces point by point and ultimately outputs an average waveform of length N, rather than R x N raw data. This mode can effectively suppress random noise and improve effective resolution.

Configuration parameters:

The average number of times R (i.e. the number of re triggers) ranges from 1 to 65535 (only in data averaging mode).

The output data format can be 16 bit or 32-bit signed integers. If 32-bit output is used, it can accommodate higher accumulation accuracy.

Theoretical improvement: According to the principle of oversampling, in order to obtain an additional n-bit resolution, R=4 ^ n averaging is required. For example, R=16 can increase the resolution by 2 bits (from 14 bits to 16 bits).

Prerequisite: The signal to be tested must have repeatability (such as periodic signals), and its amplitude and phase must remain consistent within R triggers, otherwise averaging will result in waveform distortion.

Data length limit: DataCnt can reach a maximum of 268435452 in single channel mode; The maximum in dual channel mode is 134217724 (due to alternating storage of data between the two channels).

Flexible configuration of clock and time base

5.1 Clock Architecture

The module has a built-in PLL frequency synthesizer that can accept multiple reference sources:

Internal 10 MHz crystal oscillator: accuracy ± 25 ppm, generates a 200 MHz ADC clock through PLL.

External reference clock (10 MHz): Input through CLK IN SMA, amplitude 500 mVpp~5 Vpp, 50 Ω load, PLL locked to generate 200 MHz.

External sampling clock (40 MHz~200 MHz): directly used as an ADC sampling clock, without PLL multiplication, amplitude 1 Vpp~5 Vpp, 50 Ω load.

PXI_CLK10: Backplane 10 MHz reference, delay matching<1 ns.

PXle_CK100: Backplane 100 MHz reference, delay matching<200 ps.

5.2 Sampling rate adjustment

The sampling rate is determined by dividing the Timebase frequency by the scan interval counter ScanIntrv (16 bits, 1~65535). When Timebase=200 MHz, the sampling rate range is from approximately 3.05 kS/s (200M/65535) to 200 MS/s. For example, ScanIntrv=2 yields 100 MS/s.

5.3 Timing Counter

DataCnt (28 bits): Specify the number of samples to be collected per channel (1~268435452), and pay attention to the total length limit in pre trigger/mid trigger modes.

TrigDelayTicks (16 bits): Delay triggered counter, unit time base period.

ReTrgCnt (31 bits): number of re triggers (1~2147483647), limited to 1~65535 in data averaging mode.

Multi module synchronization (including pre triggered handshake)

PXIe-9852 supports multi module synchronization through PXI Trigger Bus, and has designed a pre_data.rady handshake signal specifically for pre trigger/mid trigger modes to ensure that all slave modules have completed pre acquisition data filling before accepting the main module trigger.

6.1 Basic synchronization (post trigger/delayed trigger)

Main module: Route the internal trigger signal to a certain bit of the PXI Trigger Bus (such as TRIG0) and output the trigger pulse.

From module: Set the trigger source to the PXI Trigger Bus bit, receive the trigger, and synchronously start the acquisition.

Clock synchronization: All modules should choose the same time base source (such as PXI_CLK10 or external reference) to ensure that the sampling clock is of the same frequency and phase.

6.2 Pre trigger/mid trigger synchronization (pre_data_deady mechanism)

In pre trigger or medium trigger mode, the module needs to collect enough pre trigger samples (M) before accepting the trigger. Otherwise, the trigger will be ignored. To ensure that the main module does not send triggers in advance, the system uses the following handshake:

Each slave module working in pre trigger/mid trigger mode outputs its pre_data-ready signal to an idle PXI Trigger Bus line (such as TRIG1, TRIG2, etc.).

The main module configures these lines as inputs and logically 'correlates' with all pre_data.rady signals from the slave modules.

When all slave modules have completed pre acquisition preparation (pre_data_deady is valid), the main module is allowed to send trigger signals (via another trigger bus line).

After triggering, all modules start simultaneously and trigger or delay the collection.

This mechanism ensures the integrity of pre triggered data in a multi module system, avoiding the loss of triggers due to unprepared modules.

DMA and Data Flow

PXIe-9852 is based on PCIe Gen2 x4 interface, with a theoretical bandwidth of 2 GB/s, which is much higher than the two channel full speed data rate (about 700 MB/s). Therefore, it can achieve infinite continuous streaming disk (provided that the system storage speed is sufficient). The module uses Scatter Gather DMA to link non contiguous physical memory blocks through linked list descriptors and supports 64 bit address mapping (up to 4 GB). Each descriptor contains a PCI address, transmission length, and next pointer, and the linked list can be looped to achieve multi buffer continuous acquisition.

In non SG mode, the maximum single transfer is 8 MB; in SG mode, there is no size limit (only limited by system memory). For the data averaging mode, due to the reduction in output data volume (merging R traces into one), it is easier to achieve long-term continuous recording.

Automatic Calibration and Maintenance

8.1 Calibration constant storage

EEPROM provides two banks:

Bank 0 (read-only): Factory calibration constant, write protected.

Bank 1 (read-write): User self calibration constant.

By default, Bank 0 is loaded. Users can specify to start loading Bank 1 through software, and this setting is saved in EEPROM.

8.2 Self calibration process

Preheating: At least 20 minutes (internal temperature stable).

Preparation: Disconnect all input cables (empty load).

Operation: Call the API to perform automatic calibration, use the onboard reference source (+5V/+2.5V, temperature coefficient 3.0 ppm/° C) to correct offset and gain errors, without the need for external devices.

Result: The calibration constant is written to Bank 1 and can be selected for the next startup.

Software support

PXIe-9852 is compatible with ADLINK traditional software development kit:

WD-DASK: Supports Windows XP/7/8 drivers and DLLs, compatible with VB/VC+/BCB/Delphi and other environments.

DAQPilot: Provides APIs for languages such as VB.net/VC.net, and supports LabVIEW and MATLAB adapters.

The software is included in the ADLINK All in One CD, and unauthorized versions can be tested for 2 hours.

Typical Application Configuration Example

Distributed Temperature Sensing (DTS): using 50 Ω impedance, ± 0.2V range (high sensitivity), DC coupling, external sampling clock (synchronized with laser), and post trigger mode, ScanIntrv=1（200 MS/s）， Using data averaging mode (R=64, increase the resolution by 2 bits to 16 bits), output 32-bit data and continuously stream it to the RAID array.

Radar intermediate frequency signal: using 50 Ω, ± 2V range, AC coupling, bandwidth of 90 MHz, analog triggering (rising edge, threshold of 0.5V), medium triggering mode (pre acquisition of 2048 points, post acquisition of 8192 points), ScanIntrv=2（100 MS/s）， Single channel acquisition, triggering output to the oscilloscope for synchronization.

Multi module synchronization (4-channel): Two PXIe-9852 form a 4-channel system, with the main module triggered by external digital signals and output to PXI_TRIG0. The trigger source for the slave module is PXI_TRIG0; Both modules use PXI_CLK10 as the reference clock; If a pre trigger mode is required, the sub module outputs the pre_data_deady to PXI_TRIG1, and the main module detects the line before triggering.