Honeywell IPC 620-06 Programmable Controller

4.3 Parallel I/O Communication Mechanism

The processor broadcasts address data in parallel to all PIOMs through the I/O expansion module (IOEM).

PIOM decodes the address and generates the corresponding slot chip selection signal.

The input module locks the field signal and holds it in the input register when the chip selection is valid.

After the output instruction is solved, the processor simultaneously sends the raw data and the inverted data to the output module. The output module compares the two internally and sets the fault flag if there is a mismatch.

In the next round of ISS, the processor reads the fault flag and records the fault slot address.

This mechanism effectively detects I/O bus and module level hardware failures.

4.4 EPROM Operation and Memory Backup

When the processor module U32 socket is installed with 27128 EPROM, the system power on behavior is as follows:

Cold start (battery failure or first power on): EPROM user program, register data (4096-4351), and jump table (8192-8447) are overwritten to RAM; Clear the output status table to zero.

Hot start (battery normal): Only the EPROM user program is copied to RAM, and the output status table, registers, and jump table retain the values before power failure.

This design ensures that the accumulated value of the timer, the current value of the counter, and the hold type output are correctly restored after a brief power outage. Important: When using EPROM and permanently modifying the program, it is recommended to remove the battery for 1 minute before powering it on to force a cold start.

Instruction System and Programming Features

IPC 620-06 supports a complete ladder diagram instruction set, with instruction execution time quantified in microseconds. The main categories are as follows:

5.1 Relay Logic

Normally open/normally closed contacts, rising/falling edge trigger contacts, branching, output, hold output, latch/unlock.

5.2 Timer and Counter

0.1 second/1.0 second conduction delay, disconnection delay, and hold type conduction delay timer.

Up and down counter (counting range -65535~+65535).

5.3 Jump and Skip

Conditional skip (preserve output or force disable), jump, indirect jump, return to program start.

5.4 Sequencer

User data table storage (up to 1024 sets of 16 bit data), used to control repetitive actions or batch data storage.

5.5 Data Transmission and Arithmetic

Bring In/Send Out (16 bit I/O status or register data).

PUSH/PULL (batch transmission of multiple sets of 16 bit data).

Constant, indirect addressing.

Add, subtract, multiply, divide, compare (equal to, less than, greater than), zero detection.

5.6 Special Instructions

Input Status Scan (ISS): Users can force the insertion of a scan cycle.

Empty operation (NOP): facilitates online modification of programs.

Typical execution time: The basic contact is about 7.9-12.8 μ s, the timer is about 30-67 μ s, and the arithmetic instruction is about 72-511 μ s. The complete instruction execution schedule is shown in Table 7 of the manual.

5.7 Enhanced Run Mode Programming (ARMP)

The processor with firmware version ≥ 48 supports online program modification. The ARMP function allows adding, deleting, or editing ladder diagrams through programming terminals in RUN mode, with a maximum scan time increase of 20ms. Enabling conditions: processor in RUN/ROG, online programming enabled, watchdog timer set ≥ normal scan+20ms, programming terminal in MS-DOS 3.0 or higher, and terminal in Program mode. When ARMP is running, the system status table registers 2487-2488 display 0xAAAA, and when idle, they display 0x5555.

Diagnosis and maintenance

6.1 Self diagnostic system

Power on self-test: After the processor is reset, it automatically performs microprocessor register testing, firmware checksum, RAM read-write testing, user memory capacity detection, etc. If the RAM test fails, power off and remove the battery to clear the fault flag.

Program memory verification: The processor calculates the initial checksum of the user program during each reserved scan, and reads 24 words per scan cycle for cumulative verification during runtime. If the checksum does not match, stop scanning and place an error flag.

Online check: Verify weekly whether the first address is an ISS instruction, check the EOM position, and reset the watchdog timer (150-200ms timeout).

6.2 System Status Table

The memory address 2400-2500 area is reserved as a system state table to store critical diagnostic information, which can be read through PULL instructions or programming terminals. Common address:

Address Content

2413 Scan for lost/battery status

2415 output card fault count

2417-2431 addresses of the last 8 faulty modules

2291 Current scanning time

2295 forced I/O points

2302 processor firmware version (ARMP supported for 48 and above)

6.3 Fault Handling Strategy

Output module fault: If PIOM is set to recognize faults, the output of the rack will immediately reset (or remain) when the fault occurs, and the fault address will be stored in the status table.

Power failure: When the AC input is below 83V (115V range) or 166V (230V range) for more than 11.5ms (24VDC input is below 19V for more than 7ms), the power module broadcasts a power signal to all I/O racks, and each rack responds with the set output status.