ADLINK PXIe-9834 High Speed Digitizer Configuration Guide

3.2 Range and Data Format

The module adopts a 16 bit binary complement format, and the LSB value varies with the range:

± 10V range: LSB=0.305 mV (FSR-1LSB=9.99969 V)

±5V：0.153 mV

±1V：0.031 mV

±0.5V：0.015 mV

Positive full-scale corresponds to 0x7FFF, negative full-scale corresponds to 0x8000, and zero corresponds to 0x0000 (near the median:+1LSB=0x0001, -1LSB=0xFFFF). When programming, the driver API automatically completes the conversion between voltage and digital code.

3.3 Performance indicators (key parameters)

Signal to Noise Ratio (SNR): Typical values are 69 dB (± 0.5/± 1/± 5V range) and 65 dB (± 10V).

Total harmonic distortion (THD): -78 dB (full range).

Crosstalk: ≤ -80 dB (± 0.5V), ≤ -90 dB (± 1/± 5/± 10V), measurement conditions: 1 MHz sine wave, 90% full scale.

System noise: 0.1 mVrms at ± 0.5V range, 1.5 mVrms at ± 10V range.

Frequency response: The user manual provides typical amplitude frequency curves for impedances of 1M Ω and 50 Ω, showing a bandwidth of approximately 40 MHz at -3 dB and good passband flatness.

Trigger architecture and multi-mode detailed explanation

4.1 Overview of Trigger Sources

PXIe-9834 supports 7 types of trigger sources, which can be flexibly selected through software:

Description of minimum pulse width for triggering source signal type

Software triggers instant command - start immediately through API call

External digital trigger SMA TRG IN, TTL 3.3/5V tolerance for 20 ns rising/falling edge optional

Simulate triggering of any signal from CHO~CH3 with a 24 bit level setting for rising/falling edge condition triggering

PXI Trigger Bus [0:7] Backplane TTL 20 ns Module to Module Trigger Transmission

PXI STAR star trigger, TTL 20 ns precision low jitter trigger (issued by the system slot)

PXIe-DSTARB LVDS differential star trigger 20 ns extremely low latency (<150 ps slot to slot)

4.2 Simulation triggering details

The simulated trigger signal is obtained from the selected AI channel (CHO~CH3), independent of the acquisition channel. The trigger level is set at 16 bit resolution within the full range. Trigger condition:

Rising edge: The signal changes from below the trigger level to above the trigger level.

Falling edge: The signal changes from above the trigger level to below the trigger level.

This function does not require an external trigger line and is particularly suitable for event detection based on signal amplitude (such as partial discharge pulse triggering).

4.3 Trigger mode (timing control)

The module provides five triggering modes, covering almost all transient acquisition requirements:

Post Trigger: Collect N samples after triggering. The most common mode is used to record the response after an event occurs.

Delayed Trigger: After triggering, delay for a specified time (controlled by a 16 bit counter, with a step size of the time base period), and then collect N samples. Suitable for capturing signals with fixed delay after triggering.

Pre Trigger: Collect N samples before triggering. After initiating the pre trigger, the module continuously caches data until the triggering event arrives and stops. Used to observe a period of historical information before triggering (such as waveform before fault).

Middle Trigger: Simultaneously collect M samples before and N samples after triggering, and fully record the entire process before and after the event.

Re Trigger: In post trigger or delayed trigger mode, multiple triggering events are accepted, and a fixed number of samples are collected after each event, with all data stored continuously. The number of triggers can be set (R times, infinite if R=0). Minimum trigger interval: N+1 time base cycles in post trigger mode; In delayed triggering mode, it is (N+D)+1 time base cycle (D is the delay count). This mode is suitable for repetitive events (such as multi pulse train measurements).

Multi module synchronization (key feature)

In high channel systems such as array radar and multi-channel ultrasonic testing, multiple PXIe-9834 modules need to be synchronized. The module provides two synchronization mechanisms: trigger synchronization and time base synchronization.

5.1 Trigger synchronization

Implementing trigger signal distribution through PXI backplane:

Main module: Route internal triggers (software/external/analog) to a certain bit of PXI Trigger Bus [0.. 7] (set through software).

From module: Configure the trigger source to this bit (PXI Trigger Bus) and wait for the trigger to be received.

PXI STAR or PXIe-DSTARB can also be used, the latter having lower slot to slot skew (<150 ps), suitable for high-precision synchronization.

5.2 Time base synchronization

There are two schemes to ensure that the sampling clocks of multiple modules are of the same frequency and phase:

External reference clock: The main module or external signal source provides a 10 MHz reference clock, which is input through CLK IN and generates an 80 MHz ADC clock through onboard PLL. The same reference source can be received from the module (via backplane PXI_CLK10 or external allocation).

PXI Backplane 10 MHz: All modules can use PXI_CLK10 as a PLL reference to achieve full chassis clock synchronization without additional wiring.