ADLINK PXIe-9834 High Speed Digitizer Configuration Guide

Example of synchronous configuration:

Main module: using external digital triggering, while outputting the triggering signal to PXI_TRIG0; Time base selection internal PLL (locked to PXI_CLK10).

From module: Set the trigger source to PXI_TRIG0; The time base also selects PXI_CLK10 reference.

The sampling rate of all modules (set by the scan interval counter) must be consistent.

5.3 Synchronization precautions

When synchronizing external instruments, it is necessary to ensure that the cable lengths for triggering and clock signals match, and to add buffer drivers to reduce skew.

When synchronizing between modules, try to avoid reusing different signals on the PXI Trigger Bus to avoid conflicts.

The document provides a detailed synchronization architecture diagram (Figures 3-15 to 3-19), which engineers can refer to for configuration.

Clock and Sampling Rate Control

6.1 Internal Sampling Clock

By default, an onboard 80 MHz crystal oscillator (accuracy ± 25 ppm) is used, and frequency division sampling is achieved through a scanning interval counter (ScanIntrv), supporting any sampling rate from 1.22 kS/s to 80 MS/s (formula: sampling rate=80 MHz/ScanIntrv, ScanIntrv is 16 bits, range 1~65535). For example, setting ScanIntrv=2 yields 40 MS/s, and setting=65535 yields approximately 1.22 kS/s.

6.2 External Sampling Clock

When it is necessary to synchronize the sampling frequency with an external system (non 80 MHz integer division), an external sampling clock (frequency range of 10~80 MHz, AC coupling, 50 Ω input impedance, amplitude of 0.45~5 Vpp, duty cycle of 45%~55%) can be input through CLK IN SMA. When using an external sampling clock, it is necessary to call an API (such as WD_Config()) to reconfigure the ADC and ensure that the phase-locked loop is properly locked.

6.3 External reference clock

For applications that require strict synchronization of multiple modules, an external 10 MHz reference clock (via CLK IN) can be input, and an internal PLL can generate an 80 MHz clock. Alternatively, the PXI backplane 10 MHz (PXI_CLK10) can be directly used as a reference, which has extremely low deviation among all slots in the chassis.

DMA and Data Stream Management

The PXIe-9834 adopts PCIe Geni x4 interface, with a theoretical bandwidth of 1 GB/s (unidirectional), which is sufficient to support four channels of 80 MS/s x 16 bits=640 MB/s data flow.

7.1 Scatter‑Gather DMA

System memory is often difficult to allocate contiguous large blocks of memory. Modules support distributed aggregate DMA, which links multiple non contiguous physical memory blocks together through linked list descriptors to achieve high-capacity data transfer. Each descriptor contains a PCI address (supports 64 bits and can be mapped to over 4GB of memory), transfer length, and next descriptor pointer. The linked list can be reused to achieve multi buffer continuous acquisition (double buffer mode).

7.2 Counter Parameters

DataCnt: 31 bits, specifying the total number of samples collected (up to 2 ^ 31-1). When set to infinity, the module continuously collects data until the software stops.

TrigDelayTicks: 16 bits, used for delay triggering mode, measured in time base cycles.

Re trigger counter (ReTrgCnt): 31 bits, specifying the number of re triggers (0 means infinite).

Automatic calibration and maintenance

8.1 Calibration constant storage

PXIe-9834 is calibrated by the factory before leaving the factory, and the constant is written to Bank 0 (read-only) of the onboard EEPROM, with write protection to prevent misoperation. When the user performs self calibration, the new constant is written to Bank 1 (read-write). Default startup loading Bank 0; Users can specify the startup loading of Bank 1 through software (settings are saved in EEPROM and will not be lost upon power failure).

8.2 Self calibration process

Reason: Temperature changes and aging can cause offset and gain errors. It is recommended to perform this during the first installation of the module or when the ambient temperature changes significantly.

Requirement: Preheat for at least 20 minutes (internal temperature stable), disconnect all input cables (empty load).

Operation: Call the API to perform automatic calibration. The internal reference source of the module (1.8V/0.9V/0.45V, temperature coefficient 5 ppm/° C) is measured and path errors are corrected without the need for an external standard source.

Result: After calibration, Bank 1 is automatically updated, and the next startup can choose to load new constants.

Software ecosystem support

ADLINK provides the MAPS software suite, which includes three major components:

MAPS Core: Driver core and ACE management tool (configurable DMA buffer, device alias, and provides a soft panel for waveform preview).

MAPS/LV: LabVIEW library and examples, suitable for rapid graphical development.

MAPS/C: C/C++header files, API libraries, and examples (including trigger configuration, synchronization, data flow, etc.), suitable for high-performance customization.

All software can be downloaded from the ADLINK official website, and unauthorized versions can run in 2-hour demo mode. The commercial version requires purchasing authorization.