ADLINK PXIe-9848 High Speed Digitizer Configuration Guide

Reduce the number of working channels (for example, using only 4 channels, reducing the data rate to about 0.7 GB/s, which can meet continuous flow).

Reduce the sampling rate (by adjusting ScanIntrv).

Utilizing an onboard 512 MB FIFO as a buffer to achieve burst acquisition.

6.2 Scatter‑Gather DMA

The module supports decentralized aggregation DMA, which links non contiguous physical memory blocks together through linked list descriptors to achieve efficient transfer of large blocks of data. Each descriptor contains a 64 bit PCI address, transmission length, and next descriptor pointer. The linked list can be reused and supports continuous collection with multiple buffers. In non SG mode, the maximum single transfer is 8 MB; in SG mode, there is no size limit (only limited by system memory capacity).

6.3 Data Counter and Trigger Count

DataCnt: 32-bit, specifying the number of samples collected per channel (up to approximately 536 million).

TrigDelayTicks: 16 bits, used for delay trigger mode.

Re trigger counter (ReTrgCnt): 32-bit, set the number of re triggers (0 means infinite).

Automatic calibration and maintenance

7.1 Calibration constant storage

PXIe-9848 undergoes factory calibration before leaving the factory, with a constant written to EEPROM's Bank 0 (read-only) and write protection to prevent misoperation. When the user performs self calibration, the new constant is written to Bank 1 (read-write). By default, Bank 1 is loaded (contrary to some other models, please refer to the documentation). Users can specify to start loading Bank 0 or Bank 1 through software, and this setting is saved in EEPROM.

7.2 Self calibration process

Necessity: Temperature changes and aging can cause offset/gain drift. It is recommended to perform the module installation for the first time or when there are significant changes in ambient temperature.

Preparation: Preheat for at least 20 minutes and disconnect all input cables (empty load).

Operation: Call the API to perform automatic calibration, and the internal reference source (stable low drift) of the module is used to correct errors without external reference.

Result: The calibration constant has been updated to Bank 1 and can be used on the next startup.

Software support ecosystem

PXIe-9848 supports ADLINK traditional software development suite:

WD-DASK: Drivers and DLLs for Windows 2000/XP/Vista/7, compatible with programming environments such as VB/VC+/BCB/Delphi.

DAQPilot: Supports multiple languages under Windows (VB.net, VC.net, etc.) and provides LabVIEW and MATLAB adapters.

All software is included in the ADLINK All in One CD, and unauthorized versions can be tested for 2 hours.

Typical Application Configuration Example

Radar intermediate frequency signal capture: using 50 Ω impedance, 100MHz bandwidth, ± 2V range, DC coupling, analog triggering (rising edge, threshold 0.5V), medium triggering mode (pre acquisition of 1024 points, post acquisition of 4096 points), ScanIntrv=1（100MS/s）， Enable 4 channels, with a data rate of approximately 0.7GB/s, capable of continuous streaming.

Dynamic testing of power module: using 1M Ω impedance, 20MHz bandwidth limitation, ± 0.2V range (high sensitivity), AC coupling (removing DC bias), external digital triggering (rising edge, triggering level 1.5V), delayed triggering mode (delayed by 10 μ s), single channel acquisition, ScanIntrv=10（10MS/s）， Continuously store to SSD.

Multi module synchronization (extended from 8 channels to 16 channels): The main module sets the trigger source as an external digital trigger, and the trigger output is sent to PXI_TRIG0; All module time bases are selected as PXI_CLK10; Set the trigger source from the module to PXI_TRIG0; Unified ScanIntrv settings to ensure consistent sampling rates.