ADLINK PXIe-9848 High Speed Digitizer Configuration Guide

3.4 Range and Data Format

The module provides two ranges of ± 2V and ± 0.2V (selected through software), and 14 bit ADC data is transmitted in 16 bit binary complement format (the lower 2 bits need to be truncated, and the actual effective bits are 14 bits).

± 2V range: LSB=244.14 μ V, positive full-scale 0x7FFF corresponds to+1.999756 V, negative full-scale 0x8000 corresponds to -2 V.

± 0.2V range: LSB=24.41 μ V, corresponding to ± 0.199975 V.

When programming, the driver API automatically completes the conversion between voltage and digital code.

Trigger architecture and multi-mode acquisition

4.1 Overview of Trigger Sources

PXIe-9848 supports the following trigger sources (all channels share the same trigger source):

Key parameters of trigger source signal type

Software triggers instant commands -

External digital trigger SMA TRG IN, TTL compatible trigger level adjustable (0.8 mV~3.3 V, 12 bit step), default 1.67 V; polarity up/down optional; Minimum pulse width of 20 ns

Simulate triggering any AI channel (CHO~CH7) with a 14 bit adjustable trigger level and rising/falling edge conditions

PXI Trigger Bus [0:7] Backplane TTL Multi Module Synchronous Trigger Transmission

PX_STAR star triggered (TTL) low jitter, minimum pulse width of 20 ns

PXIe-DSTARB LVDS differential star trigger with extremely low slot to slot skew, suitable for high-precision synchronization

External digital trigger highlights: The trigger level can be programmed through software, with a range of 0.8 mV~3.3 V and a step size of 0.8 mV, greatly enhancing trigger flexibility. For example, it can be set to a threshold of 1.2 V to match specific logic levels.

4.2 Simulation triggering details

The simulated trigger signal is obtained from the selected channel without affecting the normal acquisition of that channel. The trigger level can be set at a 14 bit resolution within the full range (refer to the table), supporting rising edge (signal rising crossing trigger level) or falling edge (falling crossing trigger level) triggering.

4.3 Trigger mode (timing control)

The module provides five triggering modes, covering various transient capture requirements:

Post Trigger: Collecting N samples after triggering is the most commonly used mode.

Pre Trigger: Collect M samples before triggering to observe the signal condition before triggering (such as the waveform before the fault). After startup, the module continues to cache until a triggering event occurs.

Middle Trigger: Simultaneously collect M samples before and N samples after triggering, and fully record the process before and after the event. Note: The triggering event must occur after the pre collected data volume (M samples) is full, otherwise the triggering will be ignored.

Delayed Trigger: After triggering, a specified time (set by a 16 bit delay counter, measured in time base cycles, with a maximum delay of approximately (2 ^ 16) cycles) is delayed before collecting N samples.

Re Trigger: In post trigger or delayed trigger mode, the number of repeated triggers can be set (R times, infinite if R=0), with a fixed number of samples collected each time and all data stored continuously. The minimum interval between two triggers depends on the sampling rate and counter settings (specific formulas are not provided in the document, but it is usually necessary to ensure that the previous acquisition is completed).

4.4 Trigger Output (Multi Module Synchronization)

PXIe-9848 can serve as the main module, routing internal trigger signals (software/external/analog) to any bit of the PXI Trigger Bus to synchronize with other slave modules inside the chassis.

Clock and Time Base Control

5.1 Time Base Source Options

Internal 100 MHz oscillator: default, accuracy ± 25 ppm.

PXI_CLK10: Backplane 10 MHz reference clock, multiplied to 100 MHz through PLL, with delay matching between all slots<1 ns, suitable for single box multi module synchronization.

PXle_CK100: Backplane 100 MHz differential clock, delay matching<200 ps, suitable for higher precision synchronization.

5.2 Sampling rate adjustment

The sampling rate is fixed at 100 MS/s (based on internal time base), and downsampling is achieved through a scanning interval counter (ScanIntrv): sampling rate=100 MHz/ScanIntrv (ScanIntrv is 16 bits, with a value range of 1~65535). Therefore, the sampling rate can be continuously adjusted between approximately 1.025 kS/s (100M/65535) and 100 MS/s. For example, ScanIntrv=2 yields 50 MS/s, while ScanIntrv=3 yields 33.33 MS/s.

5.3 External Clock (This model does not directly support external sampling clock input)

The document does not mention CLK IN as an external sampling clock input, and only supports internal oscillators or backplane reference clocks (PXI_CLK10/PXle_CK100) as time base sources. The final ADC clock is fixed at 100 MHz (multiplied by PLL). Therefore, if frequency synchronization with external systems is required, it can only be achieved through reference clock synchronization (10 MHz or 100 MHz), and non 100 MHz sampling clocks cannot be directly input.

DMA and Data Stream Management

6.1 Data bandwidth challenge

100 MS/s x 14 bits per channel ≈ 1.4 Gbps, with a total data rate of approximately 11.2 Gbps (1.4 GB/s) for 8 channels. PCIe Geni x4 has a theoretical bandwidth of 1 GB/s (unidirectional), so it cannot achieve infinite continuous streaming at full speed on all channels. Solution: