ADLINK PXIe-9852 High Speed Digitizer Configuration Guide

3.3 Range and Data Format

The module supports three ranges of ± 0.2V, ± 2V, and ± 10V (software selection). 14 bit ADC data is transmitted in 16 bit binary complement format (the lower 2 bits are fixed to 0 and need to be truncated).

± 10V range: LSB=1.22 mV, positive full-scale 0x7FFC corresponds to+9.99878 V, negative full-scale 0x8000 corresponds to -10 V.

± 2V range: LSB=0.244 mV.

± 0.2V range: LSB=24.4 μ V.

The driver API automatically completes the conversion between voltage and digital code.

3.4 Performance indicators

Bandwidth: 90 MHz (typical value), the amplitude frequency curve is shown in Figure 1-1 (± 0.2Vpp) and Figure 1-2 (± 2Vpp) of the manual.

SNR: 56 dB at ± 0.2V and 62 dB at ± 2V/± 10V under 1M Ω; 60 dB at ± 0.2V and 62 dB at ± 2V under 50 Ω.

Overvoltage protection: ± 10V (1M Ω) or ± 10V sine wave/7Vrms peak<10V (50 Ω).

Trigger architecture and multi-mode acquisition

4.1 Overview of Trigger Sources

All trigger sources can be selected by software, and the trigger polarity (rising/falling) can be set:

Software trigger: API call takes effect immediately.

External digital trigger: SMA TRG IN, 3.3V TTL (5V tolerance), threshold VIH=2.0V, VIL=0.8V, minimum pulse width of 20 ns.

PX_STAR: Backplane star trigger, TTL compatible, low jitter.

PXIe-DSTARB: LVDS differential star trigger, extremely low slot to slot skew.

PXI Trigger Bus [0.. 7]: Backplane 8-bit parallel bus, which can be used for multi module trigger distribution.

Simulated trigger: Select the channel monitoring level from CH0 or CH1, and the trigger level is software adjustable (14 bit resolution).

Trigger output (TRG OUT): Whenever the acquisition starts, output a pulse synchronized with Timebase, with a programmable pulse width of 50 ns, 100 ns, 150 ns, 200 ns, 500 ns, 1 μ s, 2 μ s, 7.5 μ s, or 10 μ s, which can drive a 50 Ω load (5V TTL).

4.2 Trigger Mode

Post Trigger: Collect N samples after triggering (most commonly).

Delayed Trigger: After triggering, the data is collected after a specified delay time (set by a 16 bit delay counter with a step size of the time base period).

Pre Trigger: Collect M samples before triggering to capture the history before triggering.

Middle Trigger: Simultaneously collect M samples before triggering and N samples after triggering.

Re Trigger: In post trigger or delayed trigger mode, the number of repeated triggers R can be set (R=0 means infinite), and N samples are collected and stored continuously for each trigger. Minimum triggering interval: The post triggering mode is N+8 time base cycles; The delay triggering mode is (N+D)+8 time base cycles (D is the delay count).

4.3 Data averaging mode (core feature)

Principle: In post trigger or delayed trigger mode, if the number of re triggers R is set, the module will collect waveforms with a length of N in the R segment (N samples per trace). The data averaging mode averages R traces point by point and ultimately outputs an average waveform of length N, rather than R x N raw data. This mode can effectively suppress random noise and improve effective resolution.

Configuration parameters:

The average number of times R (i.e. the number of re triggers) ranges from 1 to 65535 (only in data averaging mode).

The output data format can be 16 bit or 32-bit signed integers. If 32-bit output is used, it can accommodate higher accumulation accuracy.

Theoretical improvement: According to the principle of oversampling, in order to obtain an additional n-bit resolution, R=4 ^ n averaging is required. For example, R=16 can increase the resolution by 2 bits (from 14 bits to 16 bits).

Prerequisite: The signal to be tested must have repeatability (such as periodic signals), and its amplitude and phase must remain consistent within R triggers, otherwise averaging will result in waveform distortion.

Data length limit: DataCnt can reach a maximum of 268435452 in single channel mode; The maximum in dual channel mode is 134217724 (due to alternating storage of data between the two channels).

Flexible configuration of clock and time base

5.1 Clock Architecture

The module has a built-in PLL frequency synthesizer that can accept multiple reference sources:

Internal 10 MHz crystal oscillator: accuracy ± 25 ppm, generates a 200 MHz ADC clock through PLL.

External reference clock (10 MHz): Input through CLK IN SMA, amplitude 500 mVpp~5 Vpp, 50 Ω load, PLL locked to generate 200 MHz.

External sampling clock (40 MHz~200 MHz): directly used as an ADC sampling clock, without PLL multiplication, amplitude 1 Vpp~5 Vpp, 50 Ω load.

PXI_CLK10: Backplane 10 MHz reference, delay matching<1 ns.

PXle_CK100: Backplane 100 MHz reference, delay matching<200 ps.

5.2 Sampling rate adjustment

The sampling rate is determined by dividing the Timebase frequency by the scan interval counter ScanIntrv (16 bits, 1~65535). When Timebase=200 MHz, the sampling rate range is from approximately 3.05 kS/s (200M/65535) to 200 MS/s. For example, ScanIntrv=2 yields 100 MS/s.

5.3 Timing Counter

DataCnt (28 bits): Specify the number of samples to be collected per channel (1~268435452), and pay attention to the total length limit in pre trigger/mid trigger modes.

TrigDelayTicks (16 bits): Delay triggered counter, unit time base period.