ADLINK PXIe-9852 High Speed Digitizer Configuration Guide

ReTrgCnt (31 bits): number of re triggers (1~2147483647), limited to 1~65535 in data averaging mode.

Multi module synchronization (including pre triggered handshake)

PXIe-9852 supports multi module synchronization through PXI Trigger Bus, and has designed a pre_data.rady handshake signal specifically for pre trigger/mid trigger modes to ensure that all slave modules have completed pre acquisition data filling before accepting the main module trigger.

6.1 Basic synchronization (post trigger/delayed trigger)

Main module: Route the internal trigger signal to a certain bit of the PXI Trigger Bus (such as TRIG0) and output the trigger pulse.

From module: Set the trigger source to the PXI Trigger Bus bit, receive the trigger, and synchronously start the acquisition.

Clock synchronization: All modules should choose the same time base source (such as PXI_CLK10 or external reference) to ensure that the sampling clock is of the same frequency and phase.

6.2 Pre trigger/mid trigger synchronization (pre_data_deady mechanism)

In pre trigger or medium trigger mode, the module needs to collect enough pre trigger samples (M) before accepting the trigger. Otherwise, the trigger will be ignored. To ensure that the main module does not send triggers in advance, the system uses the following handshake:

Each slave module working in pre trigger/mid trigger mode outputs its pre_data-ready signal to an idle PXI Trigger Bus line (such as TRIG1, TRIG2, etc.).

The main module configures these lines as inputs and logically 'correlates' with all pre_data.rady signals from the slave modules.

When all slave modules have completed pre acquisition preparation (pre_data_deady is valid), the main module is allowed to send trigger signals (via another trigger bus line).

After triggering, all modules start simultaneously and trigger or delay the collection.

This mechanism ensures the integrity of pre triggered data in a multi module system, avoiding the loss of triggers due to unprepared modules.

DMA and Data Flow

PXIe-9852 is based on PCIe Gen2 x4 interface, with a theoretical bandwidth of 2 GB/s, which is much higher than the two channel full speed data rate (about 700 MB/s). Therefore, it can achieve infinite continuous streaming disk (provided that the system storage speed is sufficient). The module uses Scatter Gather DMA to link non contiguous physical memory blocks through linked list descriptors and supports 64 bit address mapping (up to 4 GB). Each descriptor contains a PCI address, transmission length, and next pointer, and the linked list can be looped to achieve multi buffer continuous acquisition.

In non SG mode, the maximum single transfer is 8 MB; in SG mode, there is no size limit (only limited by system memory). For the data averaging mode, due to the reduction in output data volume (merging R traces into one), it is easier to achieve long-term continuous recording.

Automatic Calibration and Maintenance

8.1 Calibration constant storage

EEPROM provides two banks:

Bank 0 (read-only): Factory calibration constant, write protected.

Bank 1 (read-write): User self calibration constant.

By default, Bank 0 is loaded. Users can specify to start loading Bank 1 through software, and this setting is saved in EEPROM.

8.2 Self calibration process

Preheating: At least 20 minutes (internal temperature stable).

Preparation: Disconnect all input cables (empty load).

Operation: Call the API to perform automatic calibration, use the onboard reference source (+5V/+2.5V, temperature coefficient 3.0 ppm/° C) to correct offset and gain errors, without the need for external devices.

Result: The calibration constant is written to Bank 1 and can be selected for the next startup.

Software support

PXIe-9852 is compatible with ADLINK traditional software development kit:

WD-DASK: Supports Windows XP/7/8 drivers and DLLs, compatible with VB/VC+/BCB/Delphi and other environments.

DAQPilot: Provides APIs for languages such as VB.net/VC.net, and supports LabVIEW and MATLAB adapters.

The software is included in the ADLINK All in One CD, and unauthorized versions can be tested for 2 hours.

Typical Application Configuration Example

Distributed Temperature Sensing (DTS): using 50 Ω impedance, ± 0.2V range (high sensitivity), DC coupling, external sampling clock (synchronized with laser), and post trigger mode, ScanIntrv=1（200 MS/s）， Using data averaging mode (R=64, increase the resolution by 2 bits to 16 bits), output 32-bit data and continuously stream it to the RAID array.

Radar intermediate frequency signal: using 50 Ω, ± 2V range, AC coupling, bandwidth of 90 MHz, analog triggering (rising edge, threshold of 0.5V), medium triggering mode (pre acquisition of 2048 points, post acquisition of 8192 points), ScanIntrv=2（100 MS/s）， Single channel acquisition, triggering output to the oscilloscope for synchronization.

Multi module synchronization (4-channel): Two PXIe-9852 form a 4-channel system, with the main module triggered by external digital signals and output to PXI_TRIG0. The trigger source for the slave module is PXI_TRIG0; Both modules use PXI_CLK10 as the reference clock; If a pre trigger mode is required, the sub module outputs the pre_data_deady to PXI_TRIG1, and the main module detects the line before triggering.