GE IS200DSPXH1D Microprocessor-based Digital Signal Processor

GE IS200DSPXH1D Microprocessor-based Digital Signal Processor

Part Number IS200DSPXH1D Manufacturer General Electric Country of Manufacture As Per GE Manufacturing Policy Series EX 2100e Function Module Availability In StockIS200DSPXH1D is a Digital Signal Processor Control Board developed by GE. It is the primary controller for the Innovation Series drives' bridge, motor regulator, and gating operations. It also manages the EX2100 Excitation Control's generator field control functions. 

The logic, processing, and interface functions are all provided by the board. The DSPX board is comprised of a high-performance digital signal processor (DSP), standard memory components, and an application-specific integrated circuit (ASIC) that performs custom logic functions. Standard Hardware Features The Digital Signal Processor (DSP) of the DSPX runs at 60 MHz. There are four externals. During normal operation, the DSP receives interrupts: Stack overflow (INT0) A load pulse in the inner loop (INT1) There are two inputs that can be customized (INT2, INT3) The DSPX board supports the following types of memory: DSP boot images, code execution, configurable item storage, and system history records are all stored in FLASH memory. 

RAM is used to store data and run programs. NVRAM stands for nonvolatile random access memory. Add-only memory for identifying board revisions Both the foreground stack (from internal memory) and the background stack have overflow detection (from external SRAM). If either stack overflows, an interrupt INT0 is generated. A hard reset is generated if both stacks overflow. A configuration register is provided to disable the stack overflow reset. The DSP activates and periodically toggles a watchdog timer (toggle interval is configurable). A watchdog timer timeout will result in a hard reset. 

A free running timer of 24 bits is also provided and is used as a reference for certain functions. As two quadrature incremental tach interfaces, five differential (HIFI) pair application inputs can be used (one with marker capability). Two 16-bit up/down counters are driven by the signals. When the inputs are at the same level, it maintains its current state; when the inputs are differentially opposite, it changes state. Each time the counter increments or decrements, a 5 MHz timer resets, and a state register records the direction of the last count. A capture register is associated with each of these counters, timers, and registers and can be configured to capture the values on the occurrence of either the inner loop load pulse or the application loop load pulse. 

 The five differential HIFI inputs can be used as VCO counters in the application layer or as single-channel tach interfaces. On the differentially decoded and filtered inputs, five 16-bit counters increment. The application loop load pulse stores these counter values in registers that the DSP can read. Up to ten discrete inputs can be used in addition to the five differential HIFI inputs. Each input is filtered for three system clock cycles before being read directly by the DSP into a buffer. Custom logic in Field Programmable Gate Arrays (FPGAs) or ASICs with supporting circuits are used to provide specialized functions on the DSPX board. ASICs contain the majority of specialized and support functionality. 

 P1 has four serial interfaces, which are as follows: Two 5 Mb/s ISBusTM interfaces that can be used as master or slave One asynchronous TTL interface for a computer-based configuration tool, with RX, TX, and TXEN/RTS data signals One asynchronous TTL interface to a programmer board, including data signals RX, TX, and RTS The following functions are carried out by synchronizing load pulse signals: An inner loop load pulse signal records I/O values such as bridge, motor, or generator voltages and currents, as well as VCOs, tachometer counters, and discrete inputs. It can also synchronize ISBus channels, software, and bridge gating outputs. An application loop load pulse signal is used to capture values of other application VCOs and optionally the tachs at a sub-multiple or multiple of the inner loop load pulse. Onboard Firmware Flash memory is used to store onboard firmware. The following are the three primary types: The boot loader is responsible for the start-up sequence and should not be reloaded in the field. The application code for the drive or exciter product defines the specific control functionalities. 

The exciter's Tool port is used to load the code, while the toolbox is used to load the configuration parameters. The Unit Data Highway is used to load the exciter parameters. If applicable, drive parameters are loaded to ACL_ through a serial port, ISBus, or Ethernet. Application Data A 4-row, 128-pin DIN connector connects the DSPX board to the backplane, which is located in the board rack (P1). The DSPX is connected to another board, the EISB, in the EX2100. I/O Definitions The DSPX has three I/O connectors, which are as follows: Backplane connector P1 Port for P5 DSP emulator P6 monitoring port for engineering The P1 connector supports bridge and customer input/output (I/O) interfaces with memory-mapped process bus address space and four chip select signals. 

Individual controls are also provided for a normal UART serial interface to a programming board and a setup tool, as well as two additional ISBus proprietary serial connections for ACL or local extension features. The P5 emulator port (on the front panel of the board) connects to the TI emulator port. The P6 engineering monitor port (on the board's front panel) connects to the DSP synchronous serial port (at TTL levels) and allows connection to a GE engineering terminal only.