GE ds200ucibg3a UC2000 Motherboard

GE ds200ucibg3a UC2000 Motherboard

Part Number ds200ucibg3a Manufacturer General Electric Country of Manufacture As Per GE Manufacturing Policy Series Mark VI/VIe Function Module Availability In StockDS200UCIBG3A is a UC2000 Core Mother Board manufactured by General Electric as part of the Mark V Series used in gas turbine control systems. The connectors for connecting the host CPU daughterboard (LBC586P), two GENI boards, and a flash drive are provided by the R Core Mother Board (UCIB). The DLE gas fuel pressures from the TCSA board are translated by the UCIB board using a 196 microprocessor. 

The J1 and J3 bus connectors are used to write these signals to the LBC586P board. The J1 and J3 bus connectors are used to transfer the COREBUS and Stage Link signals written to the PANA board to the LBC586P. The LBC586P and GENI boards are installed on the UCIB Motherboard. Contains a processor with a 196-bit bus that converts serial pressure transducer signals from the TCSA board for the LBC586P. P1. Pentium processor-equipped LBC586P Daughterboard on the UCIB. The LBC586P has a daughterboard placed on it that houses the PANA board for ARCNET connections. 

P1. TCSA  Contains decoders for serial communication for Dry Low Emissions (DLE) applications between the XDSA board on the gasoline skid and the UCIB. L2. For Dry Low Emissions (DLE) applications, the Fuel Skid Interface Board (TCSA), located in the R core, communicates with the XDSA board on the fuel skid. For the 196 processors on the UCIB board, the TCSA board decodes the signals from the high-resolution pressure transducers. Position 8 of the R2> core is where the signals from XDSA are connected to the TBSA terminal board. Through the P3 connector, the TCSA board reads them. 

Decoded pressure transducer signals are written to the UCIB board via SER. UCIB CONNECTORS J1 - Bus connector that communicates with the LBC-586 and PANA boards. J2 - Connector for IDE flash drive. J3 - Bus connector that communicates with the LBC-586 and PANA boards. J4 - Routes IDE disk signals between the LBC-586 and UCIB boards. UCIB CONFIGURATION Hardware: The clock is enabled by hardware jumper JP1. For details on the hardware jumper settings for this board, consult Appendix A and the operator interface's hardware jumper panel. Software: The UCIB board has no software configuration. 

 UCIB PRESSURE TRANSDUCER INTERFACE CIRCUIT The TBSA terminal board in the R2 core receives the high-resolution pressure transducer signals from the XDSA board. The signals are received by the P3 connector on the TCSA board, which then decodes them for the 196 processor on the UCIB board to use. The J1 and J3 connectors are used to write the signals to the LBC586P board. UCIB GENIUS I/O CIRCUIT On the UCIB board, a GENI board may be installed. Certain types of data flow between the host (Mark V LM) and the Genius bus are controlled by a GENI board. On the 1TB terminal board on the "R" core, the Genius bus connections are formed. The signals are written to the LBC586P board via the P5 connector on the UCIB board and passed by the GENI board through the serial connector P3 on the UCIB board. 

The GENI board is powered by the UCIB board via the P15 connector. Many connectors on the LBC586P card are not used for the Mark V LM application. The following connections are made to the LBC-586 card: J26 - Bus connector for processor interface to memory and IO on the UCIB and PANA. J29 - Bus connector for processor interface to memory and IO on the UCIB and PANA. J18 - IDE interface connector. Ribbon cable connected to J4 on the UCIB. J7 - Power cable. Connected to P8 on the UCIB. J3 - Serial and other miscellaneous signals. Connected to P13 on the UCIB.

Features  

■ PACSystems RX7i single slot form factor.  

■ 16 Mbytes reflective memory with parity.  

■ Software configuration of all node parameters (no jumper or switch settings required).  

■ High-speed easy-to-use 2.12 Gbaud fiber-optic network.  

■ No RX7i CPU processing required to operate the network.  

■ Network-compatible with VMIC 5565 family of reflective memory devices.  

■ Connection with multimode fiber up to 300m/984.25ft.  

■ Dynamic packet sizes of 4 to 64 bytes, controlled by the Memory Xchange module.  

■ Maximum network transfer rate of 43 Mbyte/s (4 byte packets) to 174 Mbyte/s (64 byte packets)  

■ Programmable VMEbus interrupt output.  

■ Four general-purpose network interrupts with 32 bits of data each.  

■ Network error detection.  

■ Up to 256 nodes per network.  

■ Redundant transfer mode operation. This optional mode reduces the chance of a data packet being  dropped from the network.  

■ Configurable network memory offset allows you to assign nodes on a network to groups according to  the 16MB segment in the network address space that they use