ADLINK cPCI-6840 Series Single Board Computer Installation, Configuration, and Maintenance Guide

ADLINK cPCI-6840 Series 6U CompactPCI Single Board Computer: Architecture Analysis, Installation Configuration, and Engineering Application Guide

In key task areas such as industrial control, telecommunications infrastructure, military electronics, and rail transit, the 6U CompactPCI (cPCI) platform has always held a core position in embedded computing due to its high reliability, modular design, hot swappable capability, and long lifecycle support. The cPCI-6840 series single board computer (SBC) launched by ADLINK Technology is a high-performance 6U cPCI solution based on Intel Pentium M processor and 855GME/6300ESB chipset. This series not only supports 64 bit/66 MHz PCI bus, but also integrates dual PMC expansion bits, three-way Gigabit Ethernet, IPMI management controller, and rich I/O interfaces, making it an ideal choice for system upgrades and new projects in many demanding application scenarios.

Product series overview and model differentiation

The cPCI-6840 series includes two main SBC models and multiple Rear Transition Modules (RTM) to meet different front and rear I/O configuration requirements:

CPCI-6840: Standard model, equipped with two PMC stations (one above and one below), front panel without VGA/PS2 interface, suitable for displaying and keyboard mouse signals through RTM.

CPCI-6840V: The front panel comes with a DB-15 VGA interface and a PS2 keyboard/mouse combination interface, only retaining the PMC2 station above (PMC1 is occupied below), suitable for single slot applications that require front display and local control.

The matching RTM includes:

CPCI-R6840: Provides SCSI rear I/O (requires PMC-8631 SCSI PMC module) and DVI interface;

CPCI-R6841: Provides 2.5-inch HDD mounting slots, CF slots, and standard rear I/O (dual USB, dual GbE, COM2, VGA, PS2);

CPCI-R6841P: Added PIM (PMC Interface Module) socket on the basis of R6841 for rear I/O expansion of telecom PMC module.

Engineers need to combine and confirm the selection based on the functional requirements of the front and rear panels, the type of storage medium (HDD/CF/SSD), and whether SCSI or PIM expansion is needed.

Core hardware architecture and bus characteristics

1. Processor and chipset

The cPCI-6840 is equipped with the Intel Pentium M processor (μ FC-PGA2 package), with a clock speed covering 1.3 GHz to 2.0 GHz, and can be optionally equipped with low voltage (LV) or ultra-low voltage (ULV) versions (BGA package, OEM only). The processor is equipped with 1 MB or 2 MB on-chip L2 cache and a front-end bus of 400 MHz. The chipset adopts a low-power embedded combination: 855GME graphics memory controller (supporting DDR333 SDRAM, up to 2 GB, through two 200 pin SO-DIMM slots) and 6300ESB I/O controller hub, which provides dual PCI buses (64 bit/66 MHz and 32-bit/33 MHz), greatly improving I/O bandwidth.

2. CompactPCI bus interface

The core highlight is the PLX PCI-6540 three mode universal PCI-PCI bridge, which supports transparent, non transparent and universal modes. Through this bridge, cPCI-6840 can work in both system slots (as a host) and peripheral slots (as an intelligent subsystem), and complies with the PICMG 2.1 hot plug specification, supporting hot plug in peripheral slots and effectively reducing the mean time to repair (MTTR). The bridge also supports asynchronous operation of master-slave buses (such as mixing 66 MHz and 33 MHz), and is compatible with 64 bit and 32-bit data width conversion.

3. Storage interface

Primary IDE: Directly onboard 44 pin 2.5-inch HDD connector, installed in the lower PMC position (occupying PMC1).

Secondary IDE: Connected to RTM via J5 connector, RTM provides a 44 pin HDD interface and CompactFlash Type II slot (both share channels and can only be used with two devices simultaneously).

SATA: RTM provides two SATA interfaces (R6840/R6841 only), supporting a transfer rate of 150 MB/s.

4. Gigabit Ethernet

Onboard three channel GbE:

LAN1/LAN2: Using Intel 82546GB dual port controller, it is mounted on a 64 bit/66 MHz PCI bus and connected to the backplane (compliant with PICMG 2.16 packet switching backplane specification) or RTM panel (selected through the dip switch on RTM) through J3.

LAN3: Using Intel 82541PI controller, connected to 32-bit/33 MHz PCI bus, with RJ-45 interface provided on the front panel, dedicated for system management or on-site debugging.

5. Other I/O

USB 2.0: Four ports (two on the front panel and two on RTM), with 0.5 A overcurrent protection for each port.

Serial ports: COM1 (front panel RJ-45, DTE configuration) and COM2 (RTM panel RJ-45).

Video: 855GME integrated graphics card, supports analog VGA and LVDS (via J3 or RTM), cPCI-6840V front panel provides DB-15.

Jumper settings and key configurations

Proper configuration of jumpers and switches is a prerequisite for ensuring the normal operation of SBC. The following are the most critical settings:

1. JP1: Force System Slot Enable (SYSEN #)

Default (open circuit): Automatically recognize system/peripheral mode based on backplane SYSEN # signal.

Short circuit (1-2 or 2-3): Force SYSEN # to be pulled low, causing SBC to start as a system slot. Important warning: If this board is inserted into the peripheral slot but JP1 is short circuited, it may cause bus conflicts. Be cautious.