TI C2000 CLA Software Development Guide

Type 2 CLA (such as F28004x, F2838x): Supports Background Task mode. Background tasks can run continuously for communication or cleaning work, and can be preempted by high priority foreground tasks, achieving first level nesting. The code for background tasks can set an uninterruptible critical zone.

Code size limit

Type 0 CLA: The program space is 12 bit addressing, which means 4096 words (16 bits per word). All CLA instructions are 32-bit, so the maximum number of instructions is about 2048.

Type 1 and above: The program space is 16 bit addressing and can use space of up to 64K words. The starting address is configured by the interrupt vectors (MVECT1~MVECT8) corresponding to each task. The end of the task is indicated by the MSTOP instruction.

Memory and Peripheral Access Rules

CLA does not have access to all memory blocks and peripherals, and its access permissions depend on the specific device model.

Memory Access

The memory mapping table in the device data manual clearly indicates the RAM blocks that CLA can access. There are usually two types of dedicated message RAM:

CPU to CLA Message RAM: C28x read-write, CLA read-only.

CLA to CPU Message RAM: CLA is readable and writable, C28x is read-only.

In addition, certain memory blocks can be configured as CLA program storage or data storage.

Peripheral access

In the latest device family, CLA has an increasing number of peripherals that can be directly connected. Typical example:

F2803x: ADC result ePWM+HRPWM、 Comparator register.

F2806x: Add eCAP and eQEP.

F2807x/2837x: ADC module ePWM、eCAP、eQEP、 Comparator subsystem DAC、SPI、McBSP、uPP、EMIF、GPIO。

Warning: If the device contains multiple CLAs, they may be connected to different sets of peripherals. Be sure to follow the block diagram and register mapping in the device data manual.

Access arbitration priority

When C28x and CLA access the same resource (such as shared RAM or peripheral registers) simultaneously, the hardware automatically arbitrates, and the priority order is defined in the "Arbitration" section of TRM. Special attention should be paid: If C28x performs a read-write operation on a peripheral register, and CLA modifies the same register between read and write, the modification of CLA will be overwritten and lost. Therefore, the best practice is to avoid two processors writing to the same register.

Common debugging problems and solutions

CLA and C28x share the same JTAG port, and the debugging view of Code Composer Studio (CCS) will display both C28x and CLA cores simultaneously. Developers can independently pause and step through CLA code, observing registers and memory.

The following are typical faults and their troubleshooting methods:

5.1 CLA task never starts

Attempt to forcefully start the task using software and confirm that the task vector configuration is correct. If the software triggers successfully but the peripheral triggers fail, check the initialization timing of the peripheral: the CLA task only responds to the level transition edge of the interrupt source. If the peripheral generates an interrupt flag before CLA initialization, the interrupt will be missed. The solution is to clear the interrupt flag of the peripheral before initializing CLA.

Check if the task is enabled in the MIER register (EALLOW protection).

For Type 0 CLA, ensure that the task start address (MVECT register) is an offset relative to the program space first address, rather than an absolute address.

5.2 Unable to Force Tasks with Software (IACK)

Verify the following points:

The software forcing function (EALLOW protection) is enabled in the MCTL register.

The corresponding interrupt in the MIER register has been enabled.

According to the device TRM, the task trigger source has been configured as software.

The IACK parameters are correct (e.g. IACK # 0x0001 triggers task 1).

Refer to the software example in C2000Ware.

During single step debugging, after running to MSTOP, other tasks were executed

When CLA runs to MSTOP, if there are other tasks that are both in a pending state and enabled, they will automatically start executing. To avoid this phenomenon, the MIER register can be temporarily modified during debugging to prohibit all other tasks.

5.4 Variables in CLA code do not update

A common reason is that the linker command file (. cmd) allocates the. scratchpad or. bss_cola segments to read-only CLA program storage. These two segments must be placed in the readable and writable CLA data RAM, especially. scratchpad, which is used by the compiler for temporary storage. Placing them in a read-only area will result in undefined behavior.

5.5 CLA breakpoint failure after reset

The GEL file of CCS will automatically re enable the CLA clock and breakpoints during reset for debugging purposes. If you do not want this behavior, you can comment or delete the corresponding line in the GEL file.

Comparison of Depth between CLA and C28x+FPU

Many engineers are confused: since C28x also integrates FPU (Floating Point Unit), why do we still need CLA? The difference between the two lies not only in the instruction set, but also in the execution model and performance characteristics.